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US4533833A
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US
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Optically coupled integrated circuit array
Assignee: BELL TELPHONE LABORATORIES INCORPORATED A CORP OF NY
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Filing: 1982-08-19
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Granted: 1985-08-06
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Expires: 2002-08-19
Abstract
Abstract Two-dimensional semiconductor chips are stacked to form a three-dimensional array in which coupling between chips is effected optically. This permits the use of smaller chips, with a corresponding higher yield, and serves to reduce the chip area required for interconnecting leads. It also reduces the internal interconnection path lengths which, at present, limit the speed of operation.
Inventors
- 👤 John A. Copeland
- 👤 Stewart E. Miller
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 15:48
CPC Classifications
G; G02; G02B; G02B6/00; G02B6/24; G02B6/42; G02B6/43; H; H04; H04B; H04B10/00; H04B10/80; H04B10/801; H04B10/803
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
129 words
An integrated circuit array comprising: a plurality of integrated circuit chips, the plurality comprising a first chip and a second chip, each chip having a pair of broad, planar surfaces; said chips being stacked with their broad, planar surfaces substantially parallel to each other; and means for coupling between said chips, the means comprising a multiplicity of radiation sources and radiation detectors distributed among said chips, at least a first radiation source and a first radiation detector located on the first chip, and at least a second radiation source and a second radiation detector located on the second chip, such that the first radiation source can couple radiation to at least the second radiation detector, and the second radiation source can couple energy to at least the first detector.
Claim 2
Dependent Claim
129 words
An integrated circuit array comprising: a plurality of integrated circuit chips, the plurality comprising a first chip and a second chip, each chip having a pair of broad, planar surfaces; said chips being stacked with their broad, planar surfaces substantially parallel to each other; and means for coupling between said chips, the means comprising a multiplicity of radiation sources and radiation detectors distributed among said chips, at least a first radiation source and a first radiation detector located on the first chip, and at least a second radiation source and a second radiation detector located on the second chip, such that the first radiation source can couple radiation to at least the second radiation detector, and the second radiation source can couple energy to at least the first detector.
Claim 3
Dependent Claim
15 words
The array according to claim 1 wherein a heat sink separates adjacent pairs of chips.
Claim 4
Dependent Claim
16 words
The array according to claim 2 including means for coupling radiant energy through said heat sink.
Claim 5
Dependent Claim
12 words
The array according to claim 3 wherein said means is an aperture.
Claim 6
Dependent Claim
19 words
The array according to claim 3 wherein said means comprises an aperture and focussing means disposed within said aperture.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-08-05 | 1989-02-04 | 1989-08-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-08-05 | 1993-02-04 | 1993-08-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-08-05 | 1997-02-04 | 1997-08-06 | $7700.00 | Window Closed / Lapsed |