Self-routing steering network

Claim 2

A steering network having a plurality of input ports and output ports, for routing the signals on active ones of said input ports comprising: first means responsive to signal activity on said input ports for simultaneously computing binary numbers indicative of the necessary steering of said signals on said active signal ports; and second means, connected to said input ports and responsive to said first means, for steering said signals on said active signal ports to adjacent ones of said output ports.

Claim 3

The steering network of claim 1 wherein said second means steers all of said active lines simultaneously.

Claim 4

The steering network of claim 1 wherein said second means includes delay means for interposing a delay of said input signals equal to the delay incurred in said first means in computing said necessary steering.

Claim 5

A steering network for simultaneously routing input signals from a plurality of input lines, where only some of said input lines carry said input signals at any one time, to a plurality of output lines so that said input signals are grouped at adjacent ones of said output lines comprising: an adder network, responsive to said plurality of input lines, for developing a plurality of control signals corresponding to and equal in number to said plurality of input lines, each of said control signals indicating the number of said input lines away from the corresponding input line which do not carry one of said input signals; and a routing network, responsive to said plurality of control signals from said adder network and to said plurality of input lines, for routing said input signals to said output lines under direction of said plurality of control signals.

Claim 6

A steering network for simultaneously routing input signals from a plurality of input lines, where only some of said input lines carry said input signals at any one time, to a plurality of output lines so that said input signals are grouped at adjacent ones of said output lines comprising: an adder network, responsive to said plurality of input lines, for developing a plurality of control signals corresponding to and equal in number to said plurality of input lines, each of said control signals indicating the number of said input lines away from the corresponding input line which do not carry one of said input signals; and a routing network, responsive to said plurality of control signals from said adder network and to said plurality of input lines, for routing said input signals to said output lines under direction of said plurality of control signals.

Claim 7

The steering network of claim 4 wherein said adder network develops said plurality of control signals simultaneously.

Claim 8

The steering network of claim 4 wherein said routing network routes all of said input signals simultaneously.

Claim 9

The steering network of claim 4 wherein a delay network is interposed between said input lines and said routing network, said delay network delaying said input signals on said input lines by a delay equal to the delay incurred in said adder network in developing said control signals.

Claim 10

The steering network of claim 7 wherein said delay is M, where M is equal to log 2 of said plurality of input lines, rounded up.

Claim 11

The steering network of claim 4 wherein said adder network comprises: storage means for indicating which of said input lines carry said input signals, responsive to said plurality of input lines and to a strobe signal; and a plurality of adder circuits connected to said storage means and interconnected to form a matrix having a number of columns equal in number to the number of said input lines and a number of rows equal in number to log 2 of said number of said input lines, rounded up.

Claim 12

The steering network of claim 9 wherein said storage means comprises a plurality of flip-flops, each of which is connected to a different one of said input lines and to said strobe signal.

Claim 13

The steering network of claim 9, wherein said adder circuits comprise inputs A and B and output C and the interconnections among said adder circuits are defined by the equations A.sub.i,j =C.sub.i-1,j and B.sub.i,j =C.sub.i-1,j-k where i is the row, j is the column, k=2 i-1 , and connections to undefined terminals are zero.

Claim 14

The steering network of claim 4, wherein said routing network comprises a plurality of routing elements, responsive to control signals emanating from said adder network, said routing elements interconnected in successive rows and columns, with the input signals of each of said rows of routing elements being derived from output signals of the immediately preceding one of said rows of routing elements and the input signals of the first one of said rows of routing elements being derived from said delay network.

Claim 15

The steering network of claim 4, wherein said routing elements have input terminals D and E and output terminals F and G, and the interconnections among said routing elements are defined by the equations E.sub.i,j =F.sub.i-1,j and D.sub.i,j =G.sub.i-1,j+k where i is the row, j is the column, k=2 i-1 , and connections to undefined terminals are zero.

Claim 16

A steering network for simultaneously routing input signals from a plurality of input lines, where only some of said input lines carry said input signals at any one time, to a plurality of output lines so that said input signals are grouped at adjacent ones of said output lines comprising: an adder network, responsive to said plurality of input lines, for developing a plurality of control signals corresponding to and equal in number to said plurality of input lines, each of said control signals indicating the number of said input lines away from the corresponding input line which carry one of said input signals; and a routing network, responsive to said plurality of control signals from said adder network and to said plurality of input lines, for routing said input signals to said output lines under direction of said plurality of control signals.

Claim 17

A steering network for simultaneously routing input signals from a plurality of input lines, where only some of said input lines carry said input signals at any one time, to a plurality of output lines so that said input signals are grouped at adjacent ones of said output lines comprising: an adder network, responsive to said plurality of input lines, for developing a plurality of control signals corresponding to and equal in number to said plurality of input lines, each of said control signals indicating the number of said input lines away from the corresponding input line which carry one of said input signals; and a routing network, responsive to said plurality of control signals from said adder network and to said plurality of input lines, for routing said input signals to said output lines under direction of said plurality of control signals.

Claim 18

The steering network of claim 14, wherein said adder circuits comprises inputs A and B and output C and the interconnections among said adder circuits are defined by the equations A.sub.i,j =C.sub.i-1,j and B.sub.i,j =C.sub.i-1,j-k where i is the row, j is the column, k=2 i-1 , and connections to undefined terminals are zero.

Claim 19

The steering network of claim 15 wherein said routing network is an inverse perfect shuffle network, executing shuffles of said input signals under control of said plurality of control signals.

Claim 20

A steering network having N input ports and a plurality of output ports, for routing the signals on active ones of said input ports comprising: first means responsive to signal activity on said input ports for simultaneously computing binary numbers indicative of the necessary steering of said signals on said active signal ports with a processing delay of said computing being proportional to log 2 of N; and second means, connected to said input ports and responsive to said first means, for steering said signals on said active signal ports to adjacent ones of said output ports.

Claim 21

A steering network having N input ports and a plurality of output ports, for routing the signals on active ones of said input ports comprising: first means responsive to signal activity on said input ports for simultaneously computing binary numbers indicative of the necessary steering of said signals on said active signal ports with a processing delay of said computing being proportional to log 2 of N; and second means, connected to said input ports and responsive to said first means, for steering said signals on said active signal ports to adjacent ones of said output ports.

Claim 22

The steering network of claim 1 wherein said binary numbers are computed in accordance with the number of said active ones of said input ports.