Semiconductor memory device and method for manufacturing the same

Claim 1

A semiconductor memory device with a plurality of memory cells arranged in a matrix form, each of said memory cells comprising: a semiconductor region of a first conductivity type; source and drain regions of a second conductivity type formed in said semiconductor region; a gate insulation film formed on a part of said semiconductor region between said source and drain regions; a field insulation film formed on said semiconductor region for separating said memory cells from each other; an erase gate formed on said field insulation film; a floating gate formed on said gate insulation film, a portion of said floating gate overlapping a part of said erase gate with a first insulating film being interposed between said floating gate and said erase gate; and a control gate formed over said floating gate with a second insulating film being interposed between said control gate and said floating gate and said control gate being formed on said erase gate with a third insulating film being interposed between said control gate and said erase gate, said control gate thereby being insulated from said erase gate and said floating gate and overlapping the portion of said floating gate overlapping said part of said erase gate, said third insulating film being thicker than said first insulating film.