Digital memory color framing circuit

Claim 1

A color framing circuit for a digital memory, comprising: detection signal generating means for generating, on a write section of said circuit, a first detection signal to indicate which one of four color fields corresponds to a color field at a given horizontal scanning line in a vertical blanking period and for generating, on a read section of said circuit, a second detection signal to indicate a color field synchronous with a reference timing signal, when an input television signal is converted to a digital signal which is then written in said digital memory and which is thereafter read out at a timing of the reference timing signal having a different timing from that of the input television signal; means for extracting a vertical pulse in response to the reference timing signal; means for delaying the vertical pulse by a period corresponding to an odd multiple of horizontal scanning lines; means for selecting one of the vertical pulse and a delayed vertical pulse in accordance with a polarity of the second detection signal; a toggle flip-flop for loading the first detection signal as loading data read out from said memory using the vertical pulse as a load timing pulse and a horizontal pulse as a clock pulse extracted from the reference timing signal; and an address counter for receiving an output signal from said toggle flip-flop, the vertical pulse and the horizontal pulse to generate a read address signal.