US4530604A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of aligning a mask and a wafer for manufacturing semiconductor circuit elements
Assignee: Canon Inc
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Filing: 1983-08-08
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Granted: 1985-07-23
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Expires: 2003-08-08
Abstract
Abstract This specification discloses a method of aligning a mask and a wafer for manufacturing semiconductor circuit elements into a predetermined positional relationship. The method comprises two steps. In a first step, the mask and wafer are aligned by the use of relatively large alignment marks provided on the mask and wafer. In a second step, the mask and wafer are aligned by using relatively small key patterns provided on the mask and wafer and having substantially no positional deviation with respect to actual element (circuit) patterns.
Inventors
- 👤 Kazuhisa Okutsu
- 👤 Katsumi Momose
- 👤 Ryozo Hiraga
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 22:42
CPC Classifications
G; G03; G03F; G03F9/00; G03F9/70; G03F9/7073; G03F9/7076
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
134 words
A method of aligning wafers of the same type successively supported for relative parallel movement with respect to a mask, comprising the steps of: effecting rough alignment by using relatively large alignment marks provided on the mask and a first wafer; effecting fine alignment by using key patterns provided on said mask and said first wafer and having substantially no positional deviation with respect to actual element patterns; memorizing the amount of the fine alignment; supplying a second wafer of the same type as said first wafer instead of said first wafer; effecting rough alignment by using relatively large alignment marks provided on said mask and said second wafer; and moving one of said roughly aligned mask and second wafer relative and parallel to the other correspondingly to the amount of said fine alignment.
Claim 2
Independent Claim
134 words
A method of aligning wafers of the same type successively supported for relative parallel movement with respect to a mask, comprising the steps of: effecting rough alignment by using relatively large alignment marks provided on the mask and a first wafer; effecting fine alignment by using key patterns provided on said mask and said first wafer and having substantially no positional deviation with respect to actual element patterns; memorizing the amount of the fine alignment; supplying a second wafer of the same type as said first wafer instead of said first wafer; effecting rough alignment by using relatively large alignment marks provided on said mask and said second wafer; and moving one of said roughly aligned mask and second wafer relative and parallel to the other correspondingly to the amount of said fine alignment.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-07-22 | 1989-01-21 | 1989-07-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-07-22 | 1993-01-21 | 1993-07-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-07-22 | 1997-01-21 | 1997-07-23 | $7700.00 | Window Closed / Lapsed |