US4530089A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Telecommunications digital switchblock utilizing control switch state maps
Assignee: GEC PLESSEY TELECOMMUNICATIONS Ltd NEW CENTURY PARK PO BOX 53 COVENTRY CV3 1HJ
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Filing: 1983-07-26
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Granted: 1985-07-16
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Expires: 2003-07-26
Abstract
Abstract The digital switchblock includes a plurality of processor clusters which communicate via peripheral interface buffers with a number of controllers connected in serial configuration and which further communicate with the switchblock. The switchblock has a number of receive digital switching modules connected to incoming PCM transmission channels and a number of transmit digital switching modules connected to outgoing PCM transmission channels. The receive and transmit digital switching modules are interconnected by way of a plurality of control digital switching modules, to which are connected all controllers. The interconnection between one receive digital switching module and one transmit digital switching module is set up by way of one central digital switching module by use of a plurality of control switch state maps stored in the controllers. The maps depict the current state of all digital switching modules and identify a connection path through the switchblock.
Inventors
- 👤 John W. Ansell
- 👤 Thomas S. Maddern
- 👤 Alexander S. Philip
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 15:15
CPC Classifications
H; H04; H04Q; H04Q11/00; H04Q11/04; H04Q11/0407
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
164 words
A digital switchblock, for use in telecommunications equipment including a plurality of processor clusters each serially connected to a respective controller by way of a respective peripheral interface buffer, wherein the switchblock is connected for communication through PCM channels with all the controllers, and the switchblock comprises: a plurality of receive digital switching modules connected to the incoming PCM transmission channels, a plurality of transmit digital switching modules connected to the outgoing PCM transmission channels; and, a plurality of central digital switching modules to which all said controllers are connected, and arranged so that, the interconnection between one of said plurality of receive digital switching modules and one of said plurality of transmit digital switching modules is set up by way of one of said plurality of central digital switching modules by use of a plurality of control switch state maps, stored in the controllers, which depict the current state of all digital switching modules and identify a connection path through the digital switchblock.
Claim 2
Dependent Claim
164 words
A digital switchblock, for use in telecommunications equipment including a plurality of processor clusters each serially connected to a respective controller by way of a respective peripheral interface buffer, wherein the switchblock is connected for communication through PCM channels with all the controllers, and the switchblock comprises: a plurality of receive digital switching modules connected to the incoming PCM transmission channels, a plurality of transmit digital switching modules connected to the outgoing PCM transmission channels; and, a plurality of central digital switching modules to which all said controllers are connected, and arranged so that, the interconnection between one of said plurality of receive digital switching modules and one of said plurality of transmit digital switching modules is set up by way of one of said plurality of central digital switching modules by use of a plurality of control switch state maps, stored in the controllers, which depict the current state of all digital switching modules and identify a connection path through the digital switchblock.
Claim 3
Dependent Claim
95 words
A digital switchblock as claimed in claim 1 wherein a control switch state map is provided in the form of one summary map for each receive and transmit digital switching module pair which depicts the busy/idle states of the paths between the digital switching module pair and the central digital switching modules, the map includes one summary bit which represents the path to each central digital switching module which is set to indicate a busy state if there are no transmission time slots available to establish a communication path to the central digital switching module.
Claim 4
Dependent Claim
38 words
A digital switchblock as claimed in claim 2 wherein the summary maps for two corresponding receive and transmit digital switching module pairs are compared and paths are set up if the corresponding central digital switching modules are idle.
Claim 5
Dependent Claim
80 words
A digital switchblock as claimed in claim 1 wherein a control switch state map is provided, at each PCM channel location, in the form of a PCM channel ordered map including a busy bit used to indicate whether the PCM channel is in use, an identifier to indicate the transmission time slot the PCM channel is using, and a path collision bit used to indicate the possibility of a collision if a further path is connected to the PCM channel.
Claim 6
Dependent Claim
80 words
A digital switchblock as claimed in claim 1 wherein a control switch state map is provided, at each time slot location, in the form of a slot ordered map including a busy bit indicating whether the slot is in use, an identifier to indicate the PCM channel connected at the other end of the path, two reserved bits providing an indication whether go and return paths are reserved or enabled, and a link list for use with multiple connection configuration.
Claim 7
Dependent Claim
42 words
A digital switchblock as claimed in claim 1 wherein the controllers are connected in double-loop serial configuration and further controllers can be connected to the switchblock loop by breaking the loop connections between adjacent controllers and inserting and connecting the additional controller.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-07-15 | 1989-01-14 | 1989-07-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-07-15 | 1993-01-14 | 1993-07-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-07-15 | 1997-01-14 | 1997-07-16 | $7700.00 | Window Closed / Lapsed |