Patent US4530023A successfully refreshed from Google Patents.
US4530023A
Expired / Lapsed
US
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Solid state interrupt circuit
Assignee: Motorola Solutions Inc
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Filing: 1983-06-27
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Granted: 1985-07-16
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Expires: 2003-06-27
Abstract
Abstract A pair of PNPN thyristors are used to provide a solid state fuze for circuit protection. One of the pair of thyristors is self-biased on and provides normal current flow. The other thyristor turns the first thyristor off during a surge condition. A current sensing resistor is placed in series with the first thyristor to provide bias to the second transistor. The circuit will automatically reset itself when the surge condition is no longer present.
Inventors
- 👤 Leland T. Brown
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 00:47
CPC Classifications
H; H02; H02H; H02H3/00; H02H3/08; H02H3/087; Y; Y10; Y10S; Y10S323/00; Y10S323/908
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
212 words
A solid state interrupt circuit for limiting current flow when an overload condition occurs and having a first and a second terminal, comprising: a first resistor coupled to the first terminal; a first transistor having a first current carrying electrode coupled to the first resistor; a second transistor having a first current carrying electrode coupled to a control electrode of the first transistor, the second transistor further having a control electrode coupled to a second current carrying electrode of the first transistor, and having a second current carrying electrode coupled to the second terminal; a third transistor having a first current carrying electrode coupled to the first terminal, and having a control electrode and a second current carrying electrode; a fourth transistor having a first current carrying electrode coupled to the first current carrying electrode of the first transistor and coupled to the control electrode of the third transistor, the fourth transistor further having a control electrode coupled to the second current carrying electrode of the third transistor, and having a second current carrying electrode coupled to the control electrode of the first transistor; and means for providing a passive resistance coupled between the first current carrying electrode of the second transistor and the second current carrying electrode of the second transistor.
Claim 2
Dependent Claim
212 words
A solid state interrupt circuit for limiting current flow when an overload condition occurs and having a first and a second terminal, comprising: a first resistor coupled to the first terminal; a first transistor having a first current carrying electrode coupled to the first resistor; a second transistor having a first current carrying electrode coupled to a control electrode of the first transistor, the second transistor further having a control electrode coupled to a second current carrying electrode of the first transistor, and having a second current carrying electrode coupled to the second terminal; a third transistor having a first current carrying electrode coupled to the first terminal, and having a control electrode and a second current carrying electrode; a fourth transistor having a first current carrying electrode coupled to the first current carrying electrode of the first transistor and coupled to the control electrode of the third transistor, the fourth transistor further having a control electrode coupled to the second current carrying electrode of the third transistor, and having a second current carrying electrode coupled to the control electrode of the first transistor; and means for providing a passive resistance coupled between the first current carrying electrode of the second transistor and the second current carrying electrode of the second transistor.
Claim 3
Dependent Claim
210 words
The solid state interrupt circuit of claim 1 further including a second resistor coupled between the first terminal and the control electrode of the third transistor; a diode coupled from the control electrode of third transistor to the first current carrying electrodes of the first and fourth transistors; a fifth transistor having a first current carrying electrode coupled to the control electrode of the third transistor, having a control electrode coupled to the second current carrying electrode of the third transistor, and having a second current carrying electrode coupled to the means for providing a passive resistance; at least one diode coupled between the second current carrying electrodes of the fourth and fifth transistors; a sixth transistor having a first current carrying electrode coupled to the second current carrying electrode of the first transistor, having a control electrode coupled to the means for providing, and having a second current carrying electrode coupled to the second current carrying electrode of the second transistor so that the control electrode and second current carrying electrode junction of the sixth transistor is between the means for providing and the second current carrying electrode of the second transistor; and a third resistor coupled between the control electrode of the sixth transistor and the second terminal.
Claim 4
Dependent Claim
26 words
The solid state interrupt circuit of claim 1 wherein the means for providing a passive resistance is a resistor, and all the transistors are bipolar transistors.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-07-15 | 1989-01-14 | 1989-07-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-07-15 | 1993-01-14 | 1993-07-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-07-15 | 1997-01-14 | 1997-07-16 | $7700.00 | Window Closed / Lapsed |