US4529893A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Voltage comparator circuit
Assignee: TOKYO SIBAURA DENKI KK
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Filing: 1983-05-23
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Granted: 1985-07-16
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Expires: 2003-05-23
Abstract
Abstract An odd-number of pairs of differential transistors are provided. Each transistor of any pair has one control electrode and first and second terminals. An input voltage is applied to the control electrode of one of the transistors of each pair. A reference voltage is applied to the control electrode of the other transistors of each pair. The first terminals of the transistors of each pair are connected to each other, forming a node. A first load circuit is connected to the second terminal of the transistors of each odd-numbered pair whose control electrodes are connected to receive the input voltage and to the second terminal of the transistor of each even-numbered pair whose control electrode is connected to receive a reference voltage. A second load circuit is connected to the second terminal of the transistor of each even-numbered pair whose control electrode is connected to receive the input voltage and to the second terminal of the transistors of each odd-numbered pair whose control electrodes are connected to receive a reference voltage. An output transistor is driven by an output delivered from the second terminal of any transistor which is connected to the second load circuit.
Inventors
- 👤 Katsumi Nagano
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 00:21
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/22; H03K5/24; H03K5/2409; H03K5/2418; G; G01; G01R; G01R19/00; G01R19/165; G01R19/16566; G01R19/16576
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
252 words
A voltage comparator circuit comprising: an input terminal for receiving an input voltage; an odd-number of reference voltage terminals for receiving an odd-number of different reference voltages, respectively; an odd-number of pairs of differential transistors each having one control electrode and first and second terminals, the control electrodes of the differential transistors of each pair being connected to said input terminal and the corresponding reference voltage terminal and the first terminals of the differential transistors of each pair being connected to each other, forming a node; an odd-number of constant current sources provided for the pairs of differential transistors, respectively, each of said constant current sources being connected to the node of the differential transistors of the corresponding pair; a first load circuit connected to the second terminal of the differential transistor of each odd-numbered pair whose control electrode is connected to said input terminal and the second terminal of the differential transistor of each even-numbered pair whose control electrode is connected to the corresponding reference voltage terminal; a second load circuit connected to the second terminal of the differential transistor of each even-numbered pair whose control electrode is connected to said input terminal and the second terminal of the differential transistor of each odd-numbered pair whose control electrode is connected to the corresponding reference voltage terminal; and an output transistor which is connected to said second load circuit and is driven by an output delivered from the second terminal of any differential transistor which is connected to said second load circuit.
Claim 2
Dependent Claim
252 words
A voltage comparator circuit comprising: an input terminal for receiving an input voltage; an odd-number of reference voltage terminals for receiving an odd-number of different reference voltages, respectively; an odd-number of pairs of differential transistors each having one control electrode and first and second terminals, the control electrodes of the differential transistors of each pair being connected to said input terminal and the corresponding reference voltage terminal and the first terminals of the differential transistors of each pair being connected to each other, forming a node; an odd-number of constant current sources provided for the pairs of differential transistors, respectively, each of said constant current sources being connected to the node of the differential transistors of the corresponding pair; a first load circuit connected to the second terminal of the differential transistor of each odd-numbered pair whose control electrode is connected to said input terminal and the second terminal of the differential transistor of each even-numbered pair whose control electrode is connected to the corresponding reference voltage terminal; a second load circuit connected to the second terminal of the differential transistor of each even-numbered pair whose control electrode is connected to said input terminal and the second terminal of the differential transistor of each odd-numbered pair whose control electrode is connected to the corresponding reference voltage terminal; and an output transistor which is connected to said second load circuit and is driven by an output delivered from the second terminal of any differential transistor which is connected to said second load circuit.
Claim 3
Dependent Claim
33 words
A circuit according to claim 1, wherein the transistors whose second terminals are connected to one of the load circuits and whose control electrodes are connected to said input terminal are multiemitter transistors.
Claim 4
Dependent Claim
48 words
A circuit according to claim 1, wherein said first and second load circuits are a primary side transistor and a secondary side transistor which form a current mirror circuit, and the control electrode of said output transistor is connected to the second terminal of said secondary side transistor.
Claim 5
Dependent Claim
17 words
A circuit according to claim 1, wherein substantially the same current flows through said constant current sources.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-07-15 | 1989-01-14 | 1989-07-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-07-15 | 1993-01-14 | 1993-07-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-07-15 | 1997-01-14 | 1997-07-16 | $7700.00 | Window Closed / Lapsed |