Suppression of edge effects arising in CCD imager field registers

Claim 2

A CCD imager comprising: a CCD output register for performing parallel-to-series conversion, said CCD output register including a succession M in number of charge-shifting stages recurrently clocked to move charge from one stage to the next, into which charge shifting stages charge packets parallelly supplied said output register are admitted, the admission being during recurrent halts in the clocking of charge packets from each charge-shifting stage in said succession to the next, and said CCD output register further including an output stage from which is supplied response to charge packets moved from the last charge-shifting stage; a CCD imager register including at least M+2 charge transfer channels arranged side-by-side in parallel array, each charge transfer channel containing a respective succession n in number of charge-shifting stages, its charge transfer channels being recurrently clocked in unison to generate a succession of parallelly supplied charge packets, which CCD image register is of the type in which charge packets are generated in portions of its charge-shifting stages during recurrent halts in said clocking in unison, this being done by photoconversion of an optical-frequency radiant-energy image projected into each of the M+2 charge transfer channels in said parallel array; means for applying charge packets from respective outputs of the M charge transfer channels of said CCD image register that are in the middle of said M+2 charge transfer channels side-by-side in parallel array, as the charge packets parallelly supplied to respective ones of the charge-shifting stages of said CCD output register; and means for otherwise disposing of the charge packets from the respective outputs of the other charge transfer channels in said CCD image register.

Claim 3

A CCD imager as claimed in claim 1 wherein charge packets from respective outputs of the M charge transfer channels of said CCD image register that are in the middle of said M+2 charge transfer channels side-by-side in parallel array are substantially directly applied to the M successive charge-shifting stages of said CCD output register.

Claim 4

A CCD imager as claimed in claim 2 wherein said means for applying charge packets from respective outputs of the M charge transfer channels of said CCD image register that are in the middle of said M+2 charge transfer channels side-by-side in parallel array comprises: a CCD field storage register having M charge transfer channels connecting from respective ones of said middle M charge transfer channels of said CCD imager to respective ones of the charge-shifting stages of said CCD output register.

Claim 5

A CCD imager, being constructed on a substrate of long-lifetime semiconductive material having a CCD image register with a plurality of gate electrodes overspanning parallelled charge transfer channels in each of which charge carriers are generated by photoconversion responsive to a respective portion of an optical image projected into the CCD image register for illuminating at least a portion of each of said charge transfer channels; having a CCD output register with charge transfer channel into respective stages of which output charge packets from respective ones of the parallelled charge transfer channels in the image register are transferred at selected intervals in time, which output register charge transfer channel is at other intervals in time operated to provide parallel-to-series conversion of the charge packets transferred to its stages; having means responding the charge packets supplied from the output of said output register for generating an output signal; and including an improvement for eliminating edge effects in the output signal originating from the initial and final charge packets provided in each parallel-to-series converted output from said output register, which edge effects are attributable to the exchange of charge carriers between (on the one hand) each of the two side ones of the parallelled charge transfer channels in the image register respectively along the opposing sides of the image register parallel to the direction of charge transfer therethrough and (on the other hand) a portion of the semiconductor substrate outside the image register, which improvement comprises: a pair of further charge transfer channels, adjoining respective side ones of the charge transfer channels in the image register, and being arranged under the overspanning gate electrodes of the image register they flank, said further charge transfer channels being arranged to receive substantially the same illumination as the charge transfer channels they respectively adjoin; and means for discarding charge packets from the outputs of these further charge transfer channels.

Claim 6

A CCD imager, being constructed on a substrate of long-lifetime semiconductive material having a CCD image register with a plurality of gate electrodes overspanning parallelled charge transfer channels in each of which charge carriers are generated by photoconversion responsive to a respective portion of an optical image projected into the CCD image register for illuminating at least a portion of each of said charge transfer channels; having a CCD output register with charge transfer channel into respective stages of which output charge packets from respective ones of the parallelled charge transfer channels in the image register are transferred at selected intervals in time, which output register charge transfer channel is at other intervals in time operated to provide parallel-to-series conversion of the charge packets transferred to its stages; having means responding the charge packets supplied from the output of said output register for generating an output signal; and including an improvement for eliminating edge effects in the output signal originating from the initial and final charge packets provided in each parallel-to-series converted output from said output register, which edge effects are attributable to the exchange of charge carriers between (on the one hand) each of the two side ones of the parallelled charge transfer channels in the image register respectively along the opposing sides of the image register parallel to the direction of charge transfer therethrough and (on the other hand) a portion of the semiconductor substrate outside the image register, which improvement comprises: a pair of further charge transfer channels, adjoining respective side ones of the charge transfer channels in the image register, and being arranged under the overspanning gate electrodes of the image register they flank, said further charge transfer channels being arranged to receive substantially the same illumination as the charge transfer channels they respectively adjoin; and means for discarding charge packets from the outputs of these further charge transfer channels.

Claim 7

An improved CCD imager as set forth in claim 4 wherein the means for discarding charge packets from the outputs of the further ones of the charge transfer channels comprises: drain structures at the output ends of those further ones of the charge transfer channels.