US4527272A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Signature analysis using random probing and signature memory
Assignee: Tektronix Inc
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Filing: 1982-12-06
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Granted: 1985-07-02
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Expires: 2002-12-06
Abstract
Abstract A circuit test system using signature analysis allows random probing to detect faults in an assembly under test. Test points on a properly working assembly are probed at random and the signatures obtained are listed in a memory or storage media. Thereafter, when testing other boards these same test points are probed randomly and the signatures are compared to the list of possible good signatures. If a match is found a "pass" indication is generated and the operator tests another node. If a match is not found, a "failure" indication is generated and more detailed troubleshooting of circuits at that test node commences.
Inventors
- 👤 Michael G. Reiney
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 04:07
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/26; G06F11/273; G06F11/277
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
117 words
A method for testing an electronics assembly using an electronic tester, said method comprising the steps of: providing a set of data codes representing acceptable responses at a plurality of predetermined test points for testing stimulus signals provided to an operable electronic assembly of the type under test; generating a first data code in response to a testing operation on one of said plurality of predetermined test points in said electronic assembly under test; comparing said first data code to said set of data codes to determine if an equivalent data code is contained therein; and providing a test result indication in response to the comparison of said first data code to said set of data codes.
Claim 2
Independent Claim
117 words
A method for testing an electronics assembly using an electronic tester, said method comprising the steps of: providing a set of data codes representing acceptable responses at a plurality of predetermined test points for testing stimulus signals provided to an operable electronic assembly of the type under test; generating a first data code in response to a testing operation on one of said plurality of predetermined test points in said electronic assembly under test; comparing said first data code to said set of data codes to determine if an equivalent data code is contained therein; and providing a test result indication in response to the comparison of said first data code to said set of data codes.
Claim 3
Dependent Claim
69 words
A method as in claim 1 wherein the step of comparing data codes includes the steps of: scanning each of the codes of the set of data codes; comparing each of the scanned codes with said first data code; and discontinuing the scanning of the set of said data codes upon the matching of said first data code with one of the codes of said set of data codes.
Claim 4
Dependent Claim
65 words
A method as in claim 2 wherein the step of providing a test result indication includes the steps of: generating a fail indication if all of the sets of the data codes are compared with the first data code without a match being found; and generating a pass indication if a match is found for the first data code among the set of data codes.
Claim 5
Dependent Claim
64 words
A method as in claim 1 wherein the step of providing a set of data codes representing acceptable responses includes the steps of: reading a set of data codes at predetermined test points on a known electronic assembly of the type under test; and storing the data codes generated from a known operable electronic assembly of the type under test in the electronic tester.
Claim 6
Dependent Claim
61 words
A method as in claim 4 wherein the step of reading a set of data codes includes the steps of: randomly sampling the stimulus signals at predetermined test points on a known operable electronic assembly of the type under test; and generating a set of data codes in response to the randomly sampled stimulus signals of the known operable electronic assembly.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-07-01 | 1988-12-31 | 1989-07-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-07-01 | 1992-12-31 | 1993-07-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-07-01 | 1996-12-31 | 1997-07-02 | $7700.00 | Window Closed / Lapsed |