Frequency acquisition circuit for phase locked loop

Claim 2

In conjunction with a phase locked loop including an input, a controllable oscillator, and loop control circuitry, a frequency acquisition sensitive circuit comprising: a second controllable oscillator coupled to the input of the phase locked loop for altering the frequency of input signals to the phase locked loop; and means coupled to the loop control circuitry and to said second controllable oscillator for controlling said second controllable oscillator to reduce the frequency difference between the input signals to the phase locked loop and the frequency of the controllable oscillator in the phase locked loop when the frequency difference exceeds a predetermined amount and for maintaining said second controllable oscillator at a constant frequency when the frequency difference is below the predetermined value.

Claim 3

The frequency acquisition circuit of claim 1 wherein the coupled means includes a pair of comparators each having a different one of an upper and a lower predetermined amplitude signal supplied to an input thereof with a second input of each of said comparators being coupled to the loop control circuitry.

Claim 4

The frequency acquisition circuit of claim 2 wherein the coupled means further includes oscillator control circuitry coupled to supply control signals to the second controllable oscillator in response to a signal from either of the pair of comparators.

Claim 5

The frequency acquisition circuit of claim 3 wherein the oscillator control circuitry includes an up-down counter connected to activate a voltage divider network which is in turn connected to supply step function control signals to the second controllable oscillator.

Claim 6

Phase locked loop circuitry with improved acquisition sensitivity comprising: a phase locked loop including an input, a controllable oscillator, and loop control circuitry coupled to supply a control signal to the controllable oscillator; a second controllable oscillator coupled to the input of said phase locked loop for altering the frequency of input signals supplied to said phase locked loop; and means coupled to the loop control circuitry and to said second controllable oscillator for controlling said second controllable oscillator to reduce the frequency difference between the input signals to said phase locked loop and the frequency of the controllable oscillator in said phase locked loop when the frequency difference exceeds a predetermined amount and for maintaining said second controllable oscillator at a constant frequency when the frequency difference is below the predetermined amount.

Claim 7

Phase locked loop circuitry with improved acquisition sensitivity comprising: a phase locked loop including an input, a controllable oscillator, and loop control circuitry coupled to supply a control signal to the controllable oscillator; a second controllable oscillator coupled to the input of said phase locked loop for altering the frequency of input signals supplied to said phase locked loop; and means coupled to the loop control circuitry and to said second controllable oscillator for controlling said second controllable oscillator to reduce the frequency difference between the input signals to said phase locked loop and the frequency of the controllable oscillator in said phase locked loop when the frequency difference exceeds a predetermined amount and for maintaining said second controllable oscillator at a constant frequency when the frequency difference is below the predetermined amount.

Claim 8

Phase locked loop circuitry as claimed in claim 5 wherein the input signal is a PSK signal and the phase locked loop serves to demodulate the signal.

Claim 9

Phase locked loop circuitry as claimed in claim 6 wherein the input includes a mixing circuit having a first input connected to receive a phase shift keyed signal and a second input coupled to the second controllable oscillator and the coupled means is coupled to receive the control signal supplied to the controllable oscillator of the phase locked loop.