US4527117A
Expired / Lapsed
US
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Signal processing system employing charge transfer devices
Assignee: Micron Technology Inc
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Filing: 1982-10-18
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Granted: 1985-07-02
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Expires: 2002-10-18
Abstract
Abstract A signal processing system employing charge transfer devices for fast-in slow-out operation is disclosed. A push-pull input analog signal is applied to two charge transfer devices, and the clock pulses applied thereto are shifted one-half clock cycle with respect to one another. The output signals from the two charge transfer devices are differentially summed, and thereby providing cancellation of dark current and clock related noise in the charge transfer device, and doubled sample rate.
Inventors
- 👤 David W. Morgan
- 👤 Roland E. Andrews
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 20:02
CPC Classifications
G; G01; G01R; G01R13/00; G01R13/20; G01R13/22; G01R13/34; G01R13/345; G11; G11C; G11C19/00; G11C19/28; G11C19/282; G11C19/285; G11C27/00; G11C27/04
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
90 words
A signal processing system, comprising: first and second charge transfer devices for receiving a push-pull signal; a clock generator for generating clock pulses to be applied to said first and second charge transfer devices, the clock pulse for said first charge transfer device being shifted one-half clock cycle with respect to the clock pulse for said second charge transfer device so that the sampling rate of the push-pull signal is twice the clock frequency; and a differential amplifier for differentially summing the signals from said first and second charge devices.
Claim 2
Dependent Claim
90 words
A signal processing system, comprising: first and second charge transfer devices for receiving a push-pull signal; a clock generator for generating clock pulses to be applied to said first and second charge transfer devices, the clock pulse for said first charge transfer device being shifted one-half clock cycle with respect to the clock pulse for said second charge transfer device so that the sampling rate of the push-pull signal is twice the clock frequency; and a differential amplifier for differentially summing the signals from said first and second charge devices.
Claim 3
Dependent Claim
20 words
A signal processing system according to claim 1, wherein said first and second charge transfer devices are charge coupled devices.
Claim 4
Dependent Claim
25 words
A signal processing system according to claim 1, wherein the characteristics of said first and second charge transfer devices are substantially equal to each other.
Claim 5
Dependent Claim
23 words
A signal processing system according to claim 3, wherein said first and second charge transfer devices are provided in a single integrated circuit.
Claim 6
Dependent Claim
64 words
A signal processing system according to claim 2, wherein each of said first and second charge transfer devices comprises a charge injection port for sampling the input voltage and converting the sampled voltage to charge, an analog shift register for shifting the charge from said charge injection port, and an output amplifier for converting the charge from said analog shift register to a voltage.
Claim 7
Dependent Claim
164 words
A digital oscilloscope, comprising: a first amplifier for converting a single-ended input signal to a push-pull signal; first and second charge transfer devices for receiving said push-pull signal from said first amplifier; a clock generator for generating clock pulses to be applied to said first and second charge transfer devices, the clock pulse for said first charge transfer device being shifted one-half clock cycle with respect to the clock pulse for said second charge transfer device so that the sampling rate of the input signal is twice the clock frequency; a second amplifier for differentially summing the output signals from said first and second transfer devices; an analog-to-digital converter for converting the analog output signal from said second amplifier to a digital signal; a digital memory for storing the digital signal from said analog-to-digital converter; a digital-to-analog converter for converting the digital signal from said digital memory to an analog signal; and a display device for displaying the analog signal from said digital-to-analog converter.
Claim 8
Dependent Claim
164 words
A digital oscilloscope, comprising: a first amplifier for converting a single-ended input signal to a push-pull signal; first and second charge transfer devices for receiving said push-pull signal from said first amplifier; a clock generator for generating clock pulses to be applied to said first and second charge transfer devices, the clock pulse for said first charge transfer device being shifted one-half clock cycle with respect to the clock pulse for said second charge transfer device so that the sampling rate of the input signal is twice the clock frequency; a second amplifier for differentially summing the output signals from said first and second transfer devices; an analog-to-digital converter for converting the analog output signal from said second amplifier to a digital signal; a digital memory for storing the digital signal from said analog-to-digital converter; a digital-to-analog converter for converting the digital signal from said digital memory to an analog signal; and a display device for displaying the analog signal from said digital-to-analog converter.
Claim 9
Dependent Claim
34 words
A digital oscilloscope according to claim 6, wherein said clock generator changes the frequency of the clock signals from high to low in response to a trigger signal obtained from the single-ended input signal.
Claim 10
Dependent Claim
19 words
A digital oscilloscope according to claim 6, wherein said first and second charge transfer devices are charge coupled devices.
Claim 11
Dependent Claim
19 words
A digital oscilloscope according to claim 8, wherein said charge coupled devices are provided in a single integrated circuit.
References Cited (Backward Citations)
US3816815A
Cited
US3819953A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-07-01 | 1988-12-31 | 1989-07-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-07-01 | 1992-12-31 | 1993-07-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-07-01 | 1996-12-31 | 1997-07-02 | $7700.00 | Window Closed / Lapsed |