High performance and gate having an "natural" or zero threshold transistor for providing a faster rise time for the output

Claim 1

An AND gate driver circuit comprising: a NAND block having a first and second input terminals and an output node, for providing a NAND logic function voltage at said output thereof in response to the voltages applied to said input terminals; an output circuit including an enhancement mode FET device connected between a circuit output node and ground potential, having its gate connected to said output node of said NAND block; a low threshold voltage FET device connected between said circuit output node and a drain potential, having its gate connected through an impedance means to said ground potential; a substantially zero threshold voltage FET device having its source/drain path connected between said gate of said low threshold voltage FET device and a first one of said circuit inputs, and having its gate connected to a second one of said circuit inputs; said zero threshold device conducting current between said first one of said circuit inputs and said gate of said low threshold FET device when the potential of said first input begins to rise, and said zero threshold device impeding current flow between said gate of said low threshold FET device and said first one of said circuit inputs when the voltage at said circuit output node rises; whereby the rise time of the voltage at said circuit output node is reduced.