Method and circuit arrangement for synchronous detection

Claim 3

A method as claimed in claim 1, wherein the step of parity checking comprises a step of effecting modulo-two summation.

Claim 4

A method as claimed in claim 1, wherein the step of deriving the set of bits comprises a step of selecting some bits stored in said memory means in accordance with a signal generated on the basis of the result of parity checking in connection with said plurality of sets of bits.

Claim 5

A circuit arrangement for detecting synchronism of input data blocks constituting a digital signal, where each data block comprises a plurality of data words each having "n" bits, wherein "n" is a positive integer, and a parity word generated in such a manner that each bit in said parity word is given by: p.sub.m,k =a.sub.m,k ⊕b.sub.m,k ⊕ . . . wherein a m ,k, b m ,k . . . are bits in a single row of said plurality of data words; m is a positive integer and 1≦m≦n, and ⊕ indicates modulo-two summation; said "n" bits of each word being transmitted in parallel in such a manner that said digital signal comprises "n" rows, said circuit arrangement comprising: (a) first means for storing said digital signal in such a manner that said bits a m ,k, b m ,k . . . p m ,k of each row are stored according to the order of the received words; (b) second means responsive to a plurality of sets forming combinations of consecutive bits read out from said first means, the number of said consecutive bits in each set being equal to the total number of words included in each data block, the combination of bits in each set being different for each of the plurality of bits, said second means being arranged to provide respectively parity checking simultaneously in connection with said plurality of sets of bits read out from said first means each time each word is inputted to said first means; (c) third means for detecting the absence of parity error to ascertain which set of said bits does not result in parity error; and (d) fourth means for deriving a set of bits from said first means in connection with each row in accordance with the result of the detection of the absence of parity error to output the set of bits as a single row constituting a synchronized data block.

Claim 6

A circuit arrangement for detecting synchronism of input data blocks constituting a digital signal, where each data block comprises a plurality of data words each having "n" bits, wherein "n" is a positive integer, and a parity word generated in such a manner that each bit in said parity word is given by: p.sub.m,k =a.sub.m,k ⊕b.sub.m,k ⊕ . . . wherein a m ,k, b m ,k . . . are bits in a single row of said plurality of data words; m is a positive integer and 1≦m≦n, and ⊕ indicates modulo-two summation; said "n" bits of each word being transmitted in parallel in such a manner that said digital signal comprises "n" rows, said circuit arrangement comprising: (a) first means for storing said digital signal in such a manner that said bits a m ,k, b m ,k . . . p m ,k of each row are stored according to the order of the received words; (b) second means responsive to a plurality of sets forming combinations of consecutive bits read out from said first means, the number of said consecutive bits in each set being equal to the total number of words included in each data block, the combination of bits in each set being different for each of the plurality of bits, said second means being arranged to provide respectively parity checking simultaneously in connection with said plurality of sets of bits read out from said first means each time each word is inputted to said first means; (c) third means for detecting the absence of parity error to ascertain which set of said bits does not result in parity error; and (d) fourth means for deriving a set of bits from said first means in connection with each row in accordance with the result of the detection of the absence of parity error to output the set of bits as a single row constituting a synchronized data block.

Claim 7

A circuit arrangement as claimed in claim 4, wherein said first means comprises a plurality of shift registers, so that bits of each row are stored in each of said shift register in an order.

Claim 8

A circuit arrangement as claimed in claim 4, wherein said second means comprises, for each row, a plurality of parity checkers each responsive to the bits of each set.

Claim 9

A circuit arrangement as claimed in claim 4, wherein said second means comprises, for each row, an EX-OR gate responsive to said bits read out from said first means in series, and a D-flip-flop responsive to the output signal from said EX-OR gate, the output signal from said D-flip-flop being fed to an input terminal of said EX-OR gate.

Claim 12

A method as recited in claim 8 wherein said step of selecting different combinations comprises the step of inputting stored corresponding bits of 2M+1 consecutively received words to a shift register, and providing M+1 sets of output signals corresponding to each of M+1 different sequences of M+1 sequential bits in said shift register.

Claim 13

A method as recited in claim 9 wherein said step of performing a parity check comprises the step of obtaining for each of said M+1 sets a modulo-two sum of said M+1 sequential bits.

Claim 14

A method as recited in claim 10 wherein said step of selecting a combination as a synchronized received data block comprises the steps of providing to a switching circuit an output signal representative of a set of signals representing a sequence having a modulo-two sum equal to zero and controlling the switching circuit to provide as the data block an output of the M+1 words including the bits forming the sequence having the modulo-two sum equal to zero.

Claim 15

The method as recited in claim 11 wherein the step of inputting stored corresponding bits comprises the further steps of repeatedly shifting the stored bits to said shift register and for each M+1 shifts into said register enabling the switching circuit once to provide an output.

Claim 16

The method as recited in claim 11 wherein said step of inputting stored corresponding bits comprises the steps of inputting a plurality of corresponding sets of corresponding bits to a plurality of shift registers, said step of obtaining a modulo-two sum comprises the step of obtaining a modulo-two sum for each of said plurality of corresponding sets of corresponding bits, said step of providing an output signal to a switching circuit comprises the step of obtaining output signals for each of said plurality of sets of corresponding bits, and providing to said switching circuit an output signal representing a logical combination of said output signals each of which identifies a zero modulo-two sum for a common combination of bits in each of the shift registers thereby identifying the common combination as a data block.