Integrated memory matrix comprising nonvolatile reprogrammable storage cells

Claim 1

Integrated memory matrix comprising nonvolatile reprogrammable storage (memory) cells arranged in rows and columns, which are each provided with a storage transistor (Ts) from the source-drain current of which, upon selecting the address of the storage cell (M) of the storage transistor (Ts), there is derived a first voltage signal which is applied to the one input of a comparator circuit, whereas from the source-drain current of an identical reference storage transistor of like construction with respect to said storage transistor (Ts) there is derived a second voltage signal which is applied to the other input of said comparator circuit, characterized by the following features: the first input (1) of said comparator circuit (Ad) is connected to the output of a first read amplifier, with the source-drain current of said storage transistor (Ts) of said storage cell (M) flowing in the input circuit thereof, to the second input (2) of said comparator circuit (Ad) there is connected the output of a reference read amplifier (Ar) with the source-drain current of the storage transistor (Ts') of a non-programmable reference cell (Mr) of a construction identical to that of said storage cells (M), flowing in the input circuit thereof, in the circuit containing the input circuit of said reference read amplifier (Ar) and the source-drain line of said storage transistor (Ts') of said reference cell (Mr), there is arranged a first voltage source (Q1) whose voltage is adjustable in a step-by-step manner, and/or the gate electrode of said storage transistor (Ts') of said reference cell (Mr) is connected to the one terminal of a stepwisely adjustable second voltage source (Q2), and said reference read amplifier (Ar), said reference cell (Mr) and said stepwisely adjustable voltage sources (Q1, Q2) or one of said voltage sources (Q1, Q2) are/is integrated in the semiconductor body of said memory matrix (S) respectively.