Patent US4523368A successfully refreshed from Google Patents.
US4523368A
Expired / Lapsed
US
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Semiconductor devices and manufacturing methods
Assignee: Raytheon Co
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Filing: 1984-04-24
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Granted: 1985-06-18
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Expires: 2004-04-24
Abstract
Abstract A field effect device having a gate over a portion of a surface of a semiconductor disposed between a source region and a drain region and including a buried doped region having a conductivity type opposite the conductivity type of the semiconductor formed in the semiconductor under, and spaced from such portion of the surface of the semiconductor. The buried doped region is electrically connected to the gate electrode. With such arrangement a field effect device is formed with a connecting channel having a shallow depth in the semiconductor between the gate and the buried doped layer. A method for fabricating field effect devices is also disclosed, such method including the step of forming a pair of masking surfaces of insulating material on the surface of the semiconductor. An ion implantation masking layer is formed between the pair of masking surfaces to enable the selective implantation of particles in the semiconductor to establish the source and drain regions. With such method a single level of masking is used to define the source, drain and gate regions of the device.
Inventors
- 👤 Wolfgang M. Feist
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 21:04
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/80; H10D30/83; H10D30/832; H10D30/60; H10D30/611; H10D30/615; H10D30/67; H10D30/6729; H10D30/673; H10D30/6733; H10D30/674; H10D30/6757; H10D64/00; H10D64/01; H10D64/011
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
90 words
A method of forming a field effect device comprising the steps of: (a) forming a pair of spaced insulating members on the surface of a semiconductor; (b) forming a masking layer over a region of the surface of the semiconductor between the pair of spaced insulating members; (c) introducing particles to establish source and drain contact regions through portions of the surface of the semiconductor exposed by the masking layer; (d) removing the masking layer; (e) forming a gate electrode over the region between the pair of spaced insulating members.
Claim 2
Independent Claim
90 words
A method of forming a field effect device comprising the steps of: (a) forming a pair of spaced insulating members on the surface of a semiconductor; (b) forming a masking layer over a region of the surface of the semiconductor between the pair of spaced insulating members; (c) introducing particles to establish source and drain contact regions through portions of the surface of the semiconductor exposed by the masking layer; (d) removing the masking layer; (e) forming a gate electrode over the region between the pair of spaced insulating members.
Claim 3
Dependent Claim
21 words
The method recited in claim 1 wherein the semiconductor is silicon and the spaced insulating members are a compound of silicon.
Claim 4
Independent Claim
90 words
A method of forming a field effect device comprising the steps of: (a) forming a pair of spaced insulating members on the surface of a semiconductor; (b) implanting particles through the members and into the regions of the semiconductor under the pair of spaced insulating members to electrically connect source and drain regions of the device to a gate region disposed under a region of the surface of the semiconductor between the pair of spaced insulating members; and (c) forming a gate electrode between the pair of spaced insulating members.
Claim 5
Independent Claim
90 words
A method of forming a field effect device comprising the steps of: (a) forming a pair of spaced insulating members on the surface of a semiconductor; (b) implanting particles through the members and into the regions of the semiconductor under the pair of spaced insulating members to electrically connect source and drain regions of the device to a gate region disposed under a region of the surface of the semiconductor between the pair of spaced insulating members; and (c) forming a gate electrode between the pair of spaced insulating members.
Claim 6
Independent Claim
91 words
A method of forming a field effect transistor having a layer of semiconductor material formed on a surface of a substrate of insulating material with source and drain contact regions formed in upper surface portions of the semiconductor layer and a gate electrode disposed over a portion of such upper surface of the semiconductor layer between the source and drain contact regions comprising the step of forming a doped region buried within a portion of the semiconductor layer disposed beneath, spaced from, aligned with, and electrically connected to the gate electrode.
Claim 7
Independent Claim
91 words
A method of forming a field effect transistor having a layer of semiconductor material formed on a surface of a substrate of insulating material with source and drain contact regions formed in upper surface portions of the semiconductor layer and a gate electrode disposed over a portion of such upper surface of the semiconductor layer between the source and drain contact regions comprising the step of forming a doped region buried within a portion of the semiconductor layer disposed beneath, spaced from, aligned with, and electrically connected to the gate electrode.
Claim 8
Independent Claim
129 words
A method of forming a field effect transistor having a layer of semiconductor material with source and drain contact regions formed in upper surface portions of the semiconductor layer and a gate electrode disposed over such upper surface of the semiconductor layer between the source and drain contact regions, such semiconductor layer being formed on an insulating substrate, comprising the steps of: (a) forming a doped region buried within a portion of the semiconductor layer disposed beneath, spaced from, and aligned with, the gate electrode; and (b) electrically connecting the buried doped region and the gate electrode forming a conductive channel in the portion of the semiconductor between the portion of the upper surface of the semiconductor layer between the source and drain regions and the buried doped layer.
Claim 9
Independent Claim
129 words
A method of forming a field effect transistor having a layer of semiconductor material with source and drain contact regions formed in upper surface portions of the semiconductor layer and a gate electrode disposed over such upper surface of the semiconductor layer between the source and drain contact regions, such semiconductor layer being formed on an insulating substrate, comprising the steps of: (a) forming a doped region buried within a portion of the semiconductor layer disposed beneath, spaced from, and aligned with, the gate electrode; and (b) electrically connecting the buried doped region and the gate electrode forming a conductive channel in the portion of the semiconductor between the portion of the upper surface of the semiconductor layer between the source and drain regions and the buried doped layer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-06-17 | 1988-12-17 | 1989-06-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-06-17 | 1992-12-17 | 1993-06-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-06-17 | 1996-12-17 | 1997-06-18 | $7700.00 | Window Closed / Lapsed |