Three-stage binary coincidence detector apparatus with adaptive constant false alarm rate

Claim 1

A three-stage binary coincidence detector apparatus with an adaptive constant false alarm rate comprising in combination: a threshold means for establishing a first threshold level, said threshold means receiving a video signal, said threshold means receiving a range gate clock signal, said threshold means sampling said video signal at said range gate clock signal rate, said threshold means providing a logical output for each range gated video level that exceeds said first threshold level, a first counter for counting a first predetermined number of digital bits, said first counter receiving said logical output from said threshold means, said first counter means having a first predetermined binary length, said first counter recieving said range gate clock signal, said first counter providing a binary bit output every time said first predetermined number is exceeded, a second counter for counting a first predetermined number of binary bits, said second counter receiving said binary bit output from said first counter, said second counter having a second predetermined binary length, said second counter receiving said range gate clock signal, said second counter providing an alarm signal when said first predetermined number of binary bits is either equalled or exceeded, and, a threshold feedback loop connected between said first and second counters to said threshold means, said threshold feedback loop receiving a false alarm rate bias signal and an AGC signal, said threshold feedback loop receiving said alarm signal from said first counter, said threshold feedback loop providing a threshold set signal to said threshold means.