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Patent US4523213A successfully refreshed from Google Patents.
US4523213A
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MOS Semiconductor device and method of manufacturing the same
Assignee: Toshiba Corp
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Filing: 1982-07-09
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Granted: 1985-06-11
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Expires: 2002-07-09
Abstract
Abstract An MOS semiconductor device, wherein a buried region of silicon oxide or silicon nitride extends partly over the bottom plane of the channel region of an MOS transistor.
Inventors
- 👤 Masami Konaka
- 👤 Hiroshi Iwai
- 👤 Yoshio Nishi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 20:41
CPC Classifications
H; H10; H10P; H10P30/00; H10P30/20; H10P30/208; H10P30/209; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/031; H10D30/0321; H10D30/0323; H10D30/60; H10D30/67; H10D30/674; H10D30/6741; H10D30/6743; H10D30/6744; H10D62/00; H10D62/10; H10D62/113; H10D62/115; H10D62/116; H10D62/17; H10D62/351; H10D62/357; H10D62/364; H10D62/371; Y; Y10; Y10S; Y10S148/00; Y10S148/082
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
106 words
An MOS semiconductor device, which comprises: a semiconductor substrate of a first conductivity type; a source region of a second conductivity type, said source region being formed in said semiconductor substrate; a drain region of a second conductivity type, said drain region being formed in said semiconductor substrate; a short channel region disposed between said source and drain regions; a gate electrode deposited on the channel region through a gate insulation layer; and a buried solid insulating region formed in said substrate over at least a part of a bottom plane of the channel region wherein said channel region is integrally coupled with said semiconductor substrate.
Claim 2
Dependent Claim
106 words
An MOS semiconductor device, which comprises: a semiconductor substrate of a first conductivity type; a source region of a second conductivity type, said source region being formed in said semiconductor substrate; a drain region of a second conductivity type, said drain region being formed in said semiconductor substrate; a short channel region disposed between said source and drain regions; a gate electrode deposited on the channel region through a gate insulation layer; and a buried solid insulating region formed in said substrate over at least a part of a bottom plane of the channel region wherein said channel region is integrally coupled with said semiconductor substrate.
Claim 3
Dependent Claim
34 words
The MOS semiconductor device according to claim 1, wherein the buried solid insulating region is formed over a bottom plane of the drain region and partly over the bottom plane of the channel region.
Claim 4
Dependent Claim
34 words
The MOS semiconductor device according to claim 1, wherein the buried solid insulating region is formed over a bottom plane of the source region and partly over the bottom plane of the channel region.
Claim 5
Dependent Claim
43 words
The MOS semiconductor device according to claim 1, wherein the buried insulating region comprises two buried insulating regions which are formed over bottom planes of the source and drain regions, respectively, and which partially extend over the bottom plane of the channel region.
Claim 6
Dependent Claim
29 words
The MOS semiconductor device according to claim 1, wherein the buried solid insulating region comprises a single insulating region partially extending over the bottom plane of the channel region.
Claim 7
Dependent Claim
35 words
The MOS semiconductor device according to claim 1, wherein the buried solid insulating region is formed of a plurality of insulating subregions which in total partially extend over the bottom plane of the channel region.
Claim 8
Dependent Claim
32 words
The MOS semiconductor device according to any one of claims 1 to 6, wherein a field insulating layer is deposited on the semiconductor substrate to surround the source, channel and drain regions.
Claim 9
Dependent Claim
25 words
The MOS semiconductor device according to claim 7, wherein a channel stopper region of the first conductivity type is formed below the field insulating layer.
References Cited (Backward Citations)
US3514676A
Cited
US4023195A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-06-10 | 1988-12-10 | 1989-06-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-06-10 | 1992-12-10 | 1993-06-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-06-10 | 1996-12-10 | 1997-06-11 | $7700.00 | Window Closed / Lapsed |