US4523108A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Averaging circuit
Assignee: Pentax Corp
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Filing: 1982-07-21
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Granted: 1985-06-11
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Expires: 2002-07-21
Abstract
Abstract An averaging circuit includes a number of sample/hold circuits which cyclically sample/hold an input signal, the outputs of the sample hold circuits being added and applied to a comparator. A further sample/hold circuit sample/holds an internal input signal at an increased rate and the output thereof is amplified by a factor equal to the number of cyclically operated sample/hold circuits before being applied as the other input to the comparator.
Inventors
- 👤 Masaaki Niiho
- 👤 Takuo Itagaki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 10:39
CPC Classifications
G; G01; G01S; G01S17/00; G01S17/02; G01S17/06; G01S17/08; G01S17/32; G01S17/36; G01S7/00; G01S7/48; G01S7/483; G01S7/486; G01S7/4868; G01S7/487
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
107 words
An averaging circuit for processing an input signal which is intermittent and has a period, comprising, first through nth sample and hold circuit means for sampling and holding said input signal in response to sample pulses applied thereto, respectively, distribution means for generating and cyclically applying sample pulses to said first through said nth sample and hold circuit means, to cause said first through said nth sample and hold circuit means to sample said input signal during n successive periods thereof, respectively, an adder for adding the outputs of said first through nth sample and hold circuit means, wherein said distribution control circuit comprises a ring counter.
Claim 2
Dependent Claim
107 words
An averaging circuit for processing an input signal which is intermittent and has a period, comprising, first through nth sample and hold circuit means for sampling and holding said input signal in response to sample pulses applied thereto, respectively, distribution means for generating and cyclically applying sample pulses to said first through said nth sample and hold circuit means, to cause said first through said nth sample and hold circuit means to sample said input signal during n successive periods thereof, respectively, an adder for adding the outputs of said first through nth sample and hold circuit means, wherein said distribution control circuit comprises a ring counter.
Claim 3
Dependent Claim
106 words
An averaging circuit for processing an input signal which is intermittent and has a period, comprising, first through nth sample and hold circuit means for sampling and holding said input signal in response to sample pulses applied thereto respectively, distribution means for generating and cyclically applying sample pulses to said first through said nth sample and hold circuit means, to cause said first through said nth sample and hold circuit means to sample said input signal during n successive periods thereof, respectively, an adder for adding the outputs of said first through nth sample and hold circuit means, wherein said distribution control circuit comprises a microcomputer.
Claim 4
Dependent Claim
106 words
An averaging circuit for processing an input signal which is intermittent and has a period, comprising, first through nth sample and hold circuit means for sampling and holding said input signal in response to sample pulses applied thereto respectively, distribution means for generating and cyclically applying sample pulses to said first through said nth sample and hold circuit means, to cause said first through said nth sample and hold circuit means to sample said input signal during n successive periods thereof, respectively, an adder for adding the outputs of said first through nth sample and hold circuit means, wherein said distribution control circuit comprises a microcomputer.
Claim 5
Dependent Claim
148 words
A circuit for processing an input signal which is intermittent and has a period, comprising, first through nth sample and hold circuit means for sampling and holding said input signal in response to sample pulses applied thereto, respectively, distribution means for generating and cyclically applying samples pulses to said first through said nth sample and hold circuit means, to cause said first through said nth sample and hold circuit means to sample said input signal during n successive periods thereof, respectively, an adder for adding the outputs of said first through nth sample and hold circuit means, an additional sample and hold circuit means for sampling and holding a second input signal, which is intermittent and has a period, once per period of said second input signal, and means for comparing the signals held by said additional sample and hold circuit means with the output from said adder.
Claim 6
Dependent Claim
148 words
A circuit for processing an input signal which is intermittent and has a period, comprising, first through nth sample and hold circuit means for sampling and holding said input signal in response to sample pulses applied thereto, respectively, distribution means for generating and cyclically applying samples pulses to said first through said nth sample and hold circuit means, to cause said first through said nth sample and hold circuit means to sample said input signal during n successive periods thereof, respectively, an adder for adding the outputs of said first through nth sample and hold circuit means, an additional sample and hold circuit means for sampling and holding a second input signal, which is intermittent and has a period, once per period of said second input signal, and means for comparing the signals held by said additional sample and hold circuit means with the output from said adder.
Claim 7
Dependent Claim
48 words
A circuit as claimed in claim 3, wherein said means for comparing comprises an amplifier for receiving an output of said additional sample and hold circuit means, the amplification factor of said amplifier being related to the number of said first through nth sample and hold circuit means.
Claim 8
Dependent Claim
24 words
A circuit as claimed in claim 4, wherein said means for comparing further comprises comparator means receiving outputs of said amplifier and said adder.
Claim 9
Dependent Claim
43 words
A circuit as claimed in claim 3 wherein said input signal to said first through nth sample and hold circuit means and said second input signal are signals which have the same periodicity but intermittently occuring during non-overlapping times of the same period.
Claim 10
Dependent Claim
33 words
A circuit as claimed in claim 6 wherein said first and second input signals are an external light quantity signal and an internal light quantity signal, respectively, derived from an optical range finder.
References Cited (Backward Citations)
US3693100A
Cited
US3911212A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-06-10 | 1988-12-10 | 1989-06-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-06-10 | 1992-12-10 | 1993-06-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-06-10 | 1996-12-10 | 1997-06-11 | $7700.00 | Window Closed / Lapsed |