Clock distribution circuit for active aperture antenna array

Claim 2

A clock signal distribution system for synchronizing the operation of a plurality of separate digital processing elements having clock signal transmission paths of different lengths comprising: a first oscillator providing a first output frequency f 1 , a second oscillator providing a second output frequency f 2 , a phase locked oscillator adapted to receive output frequency f 1 and output frequency f 2 from said first and second oscillators respectively to provide a single combined output frequency f 1 +f 2 , a power adder having first and second inputs and an output, means for coupling said single combined output frequency f 1 +f 2 from said phase locked oscillator to said first input of said power adder, and means for coupling said output frequency f 2 from said second oscillator to said second input of said power adder, whereby a composite two-frequency clock signal is formed at the output of said power adder having sharply defined nulls occurring at the frequency f 1 .

Claim 3

Apparatus as defined in claim 1 wherein said means for coupling said output frequency f 2 from said second oscillator to said second input of said power adder includes: a phase shifter for providing a vernier adjustment of the time occurrence of the nulls in said composite two-frequency clock signal relative to said first oscillator output frequency f 1 .

Claim 4

Apparatus as defined in claim 1 wherein said means for coupling said combined output frequency f 1 +f 2 from said phase locked oscillator to said first input of said power adder includes: a phase shifter for providing a vernier adjustment of the time occurrence of the nulls in said composite two-frequency clock signal relative to said first oscillator output frequency f 1 .

Claim 5

Apparatus as defined in claim 2 and further comprising: a plurality of digital processing elements, a power divider network having an input coupled to the output of said power adder and a plurality of outputs each coupled to one of said plurality of digital processing elements.

Claim 6

Apparatus as defined in claim 4 wherein said power adder provides equal contributions of said combined output frequency f 1 +f 2 and said output frequency f 2 in said composite two-frequency clock signal.

Claim 7

Apparatus as defined in claim 1 and further comprising: a third oscillator providing a variable third output frequency f 3 , means for mixing output frequency f 1 and output frequency f 3 from said first and third oscillators respectively to provide a single combined output frequency f 1 +f 3 , delay line means coupled to said mixing means and having a plurality of output delay taps providing a like plurality of delayed output signals of frequency f 1 +f 3 , means for remixing each of said plurality of delayed output signals of frequency f 1 +f 3 with said output frequency f 3 to form a plurality of phase shifted output signals of frequency f 1 , a plurality of additional phase lock oscillators each receiving output frequency f 2 and one of said plurality of phase shifted output signals of frequency f 1 to provide a plurality of phase shifted output frequencies f 1 +f 2 , and a plurality of additional power adders each receiving an output frequency f 1 +f 2 from one of said plurality of additional phase locked oscillators and output frequency f 2 to provide a plurality of composite two-frequency clock signals having sharply defined nulls occurring at selected phases of the frequency f 1 .