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US4521736A
Expired / Lapsed
US
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Demodulator for pulse width modulated signals
Assignee: Ampex Corp
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Filing: 1979-05-09
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Granted: 1985-06-04
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Expires: 1999-05-09
Abstract
Abstract A simple demodulator circuit for demodulating high frequency pulse width modulated carrier signals, includes means for charging a capacitor to charge levels commensurate with the pulse widths. Output switch means, biased at the verge of conduction, discharge the capacitor charge at the ends of the pulses as an exponential signal with given time constant. Since the amplitudes of successive exponential signals are proportional to the respective capacitor charge levels, the charge levels are simultaneously read during the discharge process, thereby allowing demodulation at very high speeds.
Inventors
- 👤 John O. Ryan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 18:24
CPC Classifications
H; H03; H03K; H03K9/00; H03K9/08
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
98 words
A demodulator circuit for demodulating high frequency pulse width modulated signals wherein the input signal information is represented by time-variable pulse widths, comprising the combination of; capacitor means for receiving a charge which is proportional to the input pulse width; output switch means coupled to the capacitor means for enabling the capacitor to charge in the presence of an input pulse, and for reading out the capacitor charge simultaneously with enabling the capacitor to discharge upon completion of the pulse; and wherein the discharge current represents the charge received by the capacitor means and thus the demodulated signal.
Claim 2
Dependent Claim
98 words
A demodulator circuit for demodulating high frequency pulse width modulated signals wherein the input signal information is represented by time-variable pulse widths, comprising the combination of; capacitor means for receiving a charge which is proportional to the input pulse width; output switch means coupled to the capacitor means for enabling the capacitor to charge in the presence of an input pulse, and for reading out the capacitor charge simultaneously with enabling the capacitor to discharge upon completion of the pulse; and wherein the discharge current represents the charge received by the capacitor means and thus the demodulated signal.
Claim 3
Dependent Claim
47 words
The circuit of claim 1 wherein the output switch means is biased on the verge of conduction to allow the capacitor means to charge via the switch means during the presence of the pulse, and to provide the simultaneous readout during the discharge of the capacitor means.
Claim 4
Dependent Claim
66 words
The circuit of claim 1 further including; means for charging the capacitor means in proportion to the input pulse width relative to a stationary reference edge thereof; wherein the discharge current defines an exponential output signal occurring coincident with the stationary reference edge and whose magnitude corresponds to the capacitor means charge; and filter means coupled to the discharge current path for reconstituting the demodulated signal.
Claim 5
Dependent Claim
64 words
The circuit of claim 3 wherein; the means for charging includes input switch transistor means for directing current flow to the capacitor means during the duration of the pulse; and the output switch means includes output switch transistor means coupled to the capacitor means for supplying the exponential output signal to the filter means at a constant spacing equal to the stationary reference edges.
Claim 6
Dependent Claim
37 words
The circuit of claim 4 wherein the means for charging further includes a current source transistor operatively coupled to the capacitor means in response to the input transistor switch means and to the duration of the pulse.
Claim 7
Dependent Claim
36 words
The circuit of claim 5 wherein the output switch transistor means includes a pair of output transistors coupled to the capacitor means and selectively biased on the verge of conductance in the absence of a pulse.
Claim 8
Dependent Claim
43 words
The circuit of claim 6 wherein a first output transistor of the pair provides a path for the charge current in the presence of a pulse, and the second output transistor provides a path for the discharge current upon completion of the pulse.
Claim 9
Dependent Claim
46 words
The circuit of claim 7 wherein the input transistor switch means is enabled in the absence of a pulse to couple the current source transistor to ground, and is disabled during the presence of the pulse to couple the current source transistor to the capacitor means.
Claim 10
Dependent Claim
79 words
The circuit of claim 8 wherein the output switch means includes; means for biasing the output transistors; wherein the first output transistor includes an emitter coupled to the capacitor means, a base coupled to the means for biasing, and a collector coupled to a selected voltage source; and the second output transistor includes an emitter coupled to the capacitor means, a base coupled to ground, and a collector coupled to a selected voltage source and to the filter means.
References Cited (Backward Citations)
US2421025A
Cited
US3473050A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-06-03 | 1988-12-03 | 1989-06-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-06-03 | 1992-12-03 | 1993-06-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-06-03 | 1996-12-03 | 1997-06-04 | $7700.00 | Window Closed / Lapsed |