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Patent US4521725A successfully refreshed from Google Patents.
US4521725A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Series switching regulator
Assignee: RTX Corp
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Filing: 1983-12-02
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Granted: 1985-06-04
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Expires: 2003-12-02
Abstract
Abstract A switching regulator with series gated switch includes a switching bus biased positively with respect to the signal ground of the source and regulated amplitude DC signals, and PWM circuitry with associated bootstrap circuitry connected between the source DC signal input and the switching bus.
Inventors
- 👤 Charles A. Phaneuf
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 14:52
CPC Classifications
H; H02; H02M; H02M3/00; H02M3/02; H02M3/04; H02M3/10; H02M3/145; H02M3/155; H02M3/156
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
331 words
Series switching voltage regulator responsive to a source DC voltage signal received between an input terminal and signal ground, for providing a regulated amplitude DC voltage signal between an output terminal and signal ground, comprising: output filter means, including inductor means connected between the output terminal and a switching bus means; gated switch means, having a signal input connected to the source DC voltage signal at the regulator input terminal, a signal output connected to said switching bus, and a gate terminal, said gated switching means alternatively connecting and disconnecting the source DC voltage signal to said switching bus in response to a pulse width modulated (PWM) gate signal presented to said gate terminal; feedback sensing means, for providing a feedback signal indicative of the actual value of the regulated amplitude DC voltage signal; pulse width modulator means, having a low voltage potential input connected to said switching bus and a high voltage potential input responsive to high voltage potential signals provided thereto from a summing junction, said modulator means responsive to said feedback signal and said high potential signal for providing, in dependence on said feedback signal magnitude, said PWM gate signal to said switch means at a signal amplitude proportional to said high potential signal amplitude; and bootstrap circuit means, including storage capacitor means responsive to the difference voltage magnitude between said switching bus and said summing junction for storing said difference voltage therein, and signal coupling means connected between said summing junction and the regulator output terminal for maintaining said difference voltage magnitude stored in said storage capacitor means at a minimum value substantially equal to said regulated amplitude DC voltage value, said bootstrap circuit providing to said summing junction, in the presence of each of said gate signals, said high potential signal at an amplitude greater than the source DC signal amplitude, whereby said gate signal amplitude to said switch means gate terminal is greater than said source DC signal amplitude at said switch means signal input.
Claim 2
Dependent Claim
331 words
Series switching voltage regulator responsive to a source DC voltage signal received between an input terminal and signal ground, for providing a regulated amplitude DC voltage signal between an output terminal and signal ground, comprising: output filter means, including inductor means connected between the output terminal and a switching bus means; gated switch means, having a signal input connected to the source DC voltage signal at the regulator input terminal, a signal output connected to said switching bus, and a gate terminal, said gated switching means alternatively connecting and disconnecting the source DC voltage signal to said switching bus in response to a pulse width modulated (PWM) gate signal presented to said gate terminal; feedback sensing means, for providing a feedback signal indicative of the actual value of the regulated amplitude DC voltage signal; pulse width modulator means, having a low voltage potential input connected to said switching bus and a high voltage potential input responsive to high voltage potential signals provided thereto from a summing junction, said modulator means responsive to said feedback signal and said high potential signal for providing, in dependence on said feedback signal magnitude, said PWM gate signal to said switch means at a signal amplitude proportional to said high potential signal amplitude; and bootstrap circuit means, including storage capacitor means responsive to the difference voltage magnitude between said switching bus and said summing junction for storing said difference voltage therein, and signal coupling means connected between said summing junction and the regulator output terminal for maintaining said difference voltage magnitude stored in said storage capacitor means at a minimum value substantially equal to said regulated amplitude DC voltage value, said bootstrap circuit providing to said summing junction, in the presence of each of said gate signals, said high potential signal at an amplitude greater than the source DC signal amplitude, whereby said gate signal amplitude to said switch means gate terminal is greater than said source DC signal amplitude at said switch means signal input.
Claim 3
Dependent Claim
34 words
The regulator of claim 1, further comprising: preregulator means responsive to signals at said summing junction for providing said high potential signal to said modulator means high potential input at a low signal impedance.
Claim 4
Dependent Claim
32 words
The regulator of claim 1, wherein said switching bus is at a positive PWM voltage potential with respect to signal ground; and said gated switch comprises an N type field effect transistor.
Claim 5
Dependent Claim
55 words
The regulator of claim 1, wherein said feedback sensing means senses the actual value of the regulated amplitude DC voltage signal at the output terminal with respect to signal ground, and provides said feedback signal to said modulator means at a feedback signal amplitude measured with respect to said modulator means low voltage potential input.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-06-03 | 1988-12-03 | 1989-06-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-06-03 | 1992-12-03 | 1993-06-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-06-03 | 1996-12-03 | 1997-06-04 | $7700.00 | Window Closed / Lapsed |