Patent US4520458A successfully refreshed from Google Patents.
US4520458A
Expired / Lapsed
US
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Apparatus for controlling writing of data into a memory having different read and write times
Assignee: Fanuc Corp
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Filing: 1983-04-20
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Granted: 1985-05-28
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Expires: 2003-04-20
Abstract
Abstract An apparatus for controlling the writing of data from a processor into a memory having different read and write times, wherein the memory is connected directly to the processor through address and data buses without the use of an input/output port. A timer circuit is connected to the buses and memory and is controlled by the processor to produce a write timing signal which controls the writing of data into the memory. The processor is placed in a holding state, based on the write timing signal, for a period long enough to assure that the data will be written into the memory in its entirety.
Inventors
- 👤 Seiichi Hattori
- 👤 Kunio Kanda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 04:09
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/22; G06; G06F; G06F13/00; G06F13/38; G06F13/42; G06F13/4204; G06F13/4234; G06F13/4243
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
197 words
An apparatus for controlling the writing of data from a processor into a memory having different read and write times, and connected directly to the processor by address and data buses, the processor generating a timer start command signal when data is to be written into the memory in a current write cycle, comprising: a timer circuit connected to the memory and to the address and data buses, said timer circuit responsive to the timer start command signal received from the processor via the data bus, for generating a write timing signal which is applied to the memory, and for generating an enable signal, said write timing signal having a duration commensurate with the write time of the memory, so that data from the processor is written into the memory via the data bus within the write time of the memory; and a standby control circuit connected to the processor and to said timer circuit, said standby control circuit responsive to the enable signal from said timer circuit to generate a wait signal for holding the processor in the current write processing cycle long enough for the data from the processor to be written into the memory.
Claim 2
Independent Claim
197 words
An apparatus for controlling the writing of data from a processor into a memory having different read and write times, and connected directly to the processor by address and data buses, the processor generating a timer start command signal when data is to be written into the memory in a current write cycle, comprising: a timer circuit connected to the memory and to the address and data buses, said timer circuit responsive to the timer start command signal received from the processor via the data bus, for generating a write timing signal which is applied to the memory, and for generating an enable signal, said write timing signal having a duration commensurate with the write time of the memory, so that data from the processor is written into the memory via the data bus within the write time of the memory; and a standby control circuit connected to the processor and to said timer circuit, said standby control circuit responsive to the enable signal from said timer circuit to generate a wait signal for holding the processor in the current write processing cycle long enough for the data from the processor to be written into the memory.
Claim 3
Dependent Claim
51 words
The apparatus according to claim 1, wherein said timer circuit supplies said standby control circuit with a disable signal when the writing of the data into the memory is completed, said standby control circuit responding by terminating the wait signal to free the processor for execution of a subsequent processing cycle.
Claim 4
Independent Claim
269 words
An apparatus for controlling writing of data from a processor into a memory having different read and write times, the processor providing a timer start command signal and address memory at which the data is to be written during a current write processing cycle, comprising: an address bus, directly connected to the processor and the memory, for providing the address at which the data is to be written into the memory; a data bus, directly connected the processor and the memory, for providing the timer start command signal and the data which is to be written into the memory; a timer circuit, connected to the memory, said address bus and said data bus, for sending a write timing signal to the memory in response to the timer start command signal and for generating an enable signal, said write timing signal having a duration which is at least as long as the write time of the memory, so that the data provided by the processor on said data bus is written into the memory within the write time; and a standby control circuit, connected to the processor and said timer circuit, for providing a wait signal to the processor in response to the enable signal generated by said timer circuit, the wait signal holding the processor in the current write processing cycle until the data provided on the data bus by the processor is written into the memory, said standby control circuit ceasing generation of the wait signal when said timer circuit stops generating the enable signal, so that the processor is allowed to execute the next write processing cycle.
Claim 5
Independent Claim
269 words
An apparatus for controlling writing of data from a processor into a memory having different read and write times, the processor providing a timer start command signal and address memory at which the data is to be written during a current write processing cycle, comprising: an address bus, directly connected to the processor and the memory, for providing the address at which the data is to be written into the memory; a data bus, directly connected the processor and the memory, for providing the timer start command signal and the data which is to be written into the memory; a timer circuit, connected to the memory, said address bus and said data bus, for sending a write timing signal to the memory in response to the timer start command signal and for generating an enable signal, said write timing signal having a duration which is at least as long as the write time of the memory, so that the data provided by the processor on said data bus is written into the memory within the write time; and a standby control circuit, connected to the processor and said timer circuit, for providing a wait signal to the processor in response to the enable signal generated by said timer circuit, the wait signal holding the processor in the current write processing cycle until the data provided on the data bus by the processor is written into the memory, said standby control circuit ceasing generation of the wait signal when said timer circuit stops generating the enable signal, so that the processor is allowed to execute the next write processing cycle.
References Cited (Backward Citations)
US4092728A
Cited
US4388695A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-05-27 | 1988-11-26 | 1989-05-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-05-27 | 1992-11-26 | 1993-05-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-05-27 | 1996-11-26 | 1997-05-28 | $7700.00 | Window Closed / Lapsed |