Patent US4520437A successfully refreshed from Google Patents.
US4520437A
Expired / Lapsed
US
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Power conversion circuit for synthesizing a sinewave with programmed amplitude control
Assignee: Nokia Bell Labs
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Filing: 1983-07-14
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Granted: 1985-05-28
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Expires: 2003-07-14
Abstract
Abstract A waveform synthesizer is controlled in response to a stored program control utilizing tabular data stored in memory as the basis for generating timing signals to drive the power switching devices of the synthesizer. A plurality of tables of differing modulation indices define rated current output and a below rated current output. The table defines rated level output timing signals as both pulse width and frequency modulated to reduce harmonics. Various overload conditions result in selection of different modulation indices or a total current shutdown. A high peak current overload results in a halt in a progressive upward selection of modulation indices during start-up. A high average current overload results in a reduction in modulation indices until the overload has cleared. A low converter voltage signal caused by current limiting in the converter is detected and also used to reduce the modulation index so that less DC current is drawn from the converter and operation is maintained near the maximum average output power capability of the converter.
Inventors
- 👤 Charles W. Boettcher, Jr.
- 👤 Billy H. Hamilton
- 👤 William M. Slak
- 👤 Walter L. Zweig
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 20:40
CPC Classifications
H; H02; H02M; H02M7/00; H02M7/42; H02M7/44; H02M7/48; H02M7/53; H02M7/537; H02M7/5387; H02M7/53871; H02M7/53873
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
209 words
A power conversion circuit for synthesizing a low frequency sinewave signal; input means for accepting a source of energy, means for converting the energy at the input means into a pulse carrier signal, means for modulating the pulse carrier signal by supplying timing signals to the means for converting, comprising: means for generating timing signals, including: a data processor under stored program control, a memory including a stored program for controlling the processor and a plurality of tables including timing signal data, each table being responsible for producing a different output sinewave signal amplitude, whereby the stored program selects one of the plurality of tables and utilizes its timing signal data for generating timing signals operative for modulating the pulse carrier output means for coupling to a load and including filtering means, means for detecting an average current overload condition, means for limiting average current output responsive to the means for detecting including: instructions in the stored program for selecting a different one of the plurality of tables of timing signal data for reducing an amplitude of the output sinewave signal and continuing to select different ones of the plurality of tables to successively reduce amplitude of the output sinewave signal until the average current overload condition is corrected.
Claim 2
Dependent Claim
209 words
A power conversion circuit for synthesizing a low frequency sinewave signal; input means for accepting a source of energy, means for converting the energy at the input means into a pulse carrier signal, means for modulating the pulse carrier signal by supplying timing signals to the means for converting, comprising: means for generating timing signals, including: a data processor under stored program control, a memory including a stored program for controlling the processor and a plurality of tables including timing signal data, each table being responsible for producing a different output sinewave signal amplitude, whereby the stored program selects one of the plurality of tables and utilizes its timing signal data for generating timing signals operative for modulating the pulse carrier output means for coupling to a load and including filtering means, means for detecting an average current overload condition, means for limiting average current output responsive to the means for detecting including: instructions in the stored program for selecting a different one of the plurality of tables of timing signal data for reducing an amplitude of the output sinewave signal and continuing to select different ones of the plurality of tables to successively reduce amplitude of the output sinewave signal until the average current overload condition is corrected.
Claim 3
Dependent Claim
53 words
A power conversion circuit as defined in claim 1 wherein the means for detecting further includes low peak current detection means and the stored program control being operative for disabling a selection of progressive tabular values said remaining fixed at a present tabulated index value at which a low peak current is detected.
Claim 4
Dependent Claim
65 words
A power conversion circuit as defined in claim 2 wherein a low voltage detector is coupled to detect a drop in voltage at the source of energy coupled to the input means, means, responsive to the low voltage detector for gating a signal to the means for modulating the pulse carrier signal, which signal is operative for changing the table used to generate timing signals.
Claim 5
Dependent Claim
230 words
A circuit for synthesizing a sinewave signal comprising: means for generating a pulse carrier signal including: a processor under control of a stored program, a memory including the stored program and a plurality of table of modulation index values, means for monitoring output signal conditions means for activating the stored program to select one of the tables of modulation index values in order to control a magnitude of an output signal in response to a signal from the means for monitoring, the processor and stored program utilizing a selected table of modulating index values to generate timing signals, at least one of the tables of modulation index values having values to permit generation of timing pulses that simultaneously pulse width modulate and frequency modulate the pulse carrier signal whereby the pulse carrier is pulse width modulated so that a net area value of pulses for a particular time interval substantially equals an amplitude value of a sinewave signal to be synthesized at a particular time interval, and is frequency modulated so that the pulse carrier signal continuously changes in frequency from a high limit frequency at points in time when the sinewave signal crosses its zero axis to a low limit frequency at a peak value of an amplitude of the sinewave signal, and means for deriving a smooth synthesized sinewave signal from the pulse carrier signal as so modulated.
Claim 6
Dependent Claim
230 words
A circuit for synthesizing a sinewave signal comprising: means for generating a pulse carrier signal including: a processor under control of a stored program, a memory including the stored program and a plurality of table of modulation index values, means for monitoring output signal conditions means for activating the stored program to select one of the tables of modulation index values in order to control a magnitude of an output signal in response to a signal from the means for monitoring, the processor and stored program utilizing a selected table of modulating index values to generate timing signals, at least one of the tables of modulation index values having values to permit generation of timing pulses that simultaneously pulse width modulate and frequency modulate the pulse carrier signal whereby the pulse carrier is pulse width modulated so that a net area value of pulses for a particular time interval substantially equals an amplitude value of a sinewave signal to be synthesized at a particular time interval, and is frequency modulated so that the pulse carrier signal continuously changes in frequency from a high limit frequency at points in time when the sinewave signal crosses its zero axis to a low limit frequency at a peak value of an amplitude of the sinewave signal, and means for deriving a smooth synthesized sinewave signal from the pulse carrier signal as so modulated.
Claim 7
Dependent Claim
56 words
A circuit for synthesizing a sinewave signal as defined in claim 4 where the plurality of tables of modulation index values define a plurality of waveforms having a series of amplitudes below and at a rated value, and the stored program includes instructions for selecting a progression of tabulated index values during start-up of the circuit.
Claim 8
Dependent Claim
102 words
A circuit for synthesizing a sinewave signal as defined in claim 5 further including means for detecting an overload condition having a high peak threshold, a peak threshold less than the surge threshold, and a continuous average overcurrent condition, the stored program controller responsive to the means for detecting and operative to shut down the means for generating when a high peak threshold is attained, prevent continued progressive selection of a succession of modulation index tables at start-up if a low peak threshold is attained, and to selectively reduce a level of modulation index tables until an average overcurrent condition is corrected.
Claim 9
Dependent Claim
35 words
A circuit for synthesizing a sinewave signal as defined in claim 5 wherein the stored program selects a progressive set of modulation index tables at start-up so that the synthesized sinewave slowly increases in amplitude.
Claim 10
Dependent Claim
46 words
A circuit for synthesizing a sinewave signal as defined in claim 7 wherein the stored program monitors a source of enabling energy applied to the means for generating a pulse carrier signal and prevents it from starting until the source of enabling energy is deemed stabilized.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-05-27 | 1988-11-26 | 1989-05-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-05-27 | 1992-11-26 | 1993-05-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-05-27 | 1996-11-26 | 1997-05-28 | $7700.00 | Window Closed / Lapsed |