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US4520347A
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Code conversion circuit
Assignee: Motorola Solutions Inc
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Filing: 1982-11-22
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Granted: 1985-05-28
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Expires: 2002-11-22
Abstract
Abstract A code conversion circuit comprising logic for converting an n-bit binary number having a sign bit in two's complement code to sign-magnitude code is provided where n is an integer. The logic identifies whether or not the binary number is positive or negative. Regardless of polarity, the sign bit and least significant bit are directly outputted. If the binary number is positive, all bits are outputted with unchanged logic states. If the binary number is negative, the least significant bit of the n magnitude bits which has a logic one value is identified. The remaining n magnitude bits of higher significance are inverted and outputted with the other magnitude bits.
Inventors
- 👤 Jules D. Campbell, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 08:17
CPC Classifications
H; H03; H03M; H03M7/00; H03M7/02; H03M7/04
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
268 words
A code conversion circuit, for converting an n-bit binary number having a sign bit and n-1 magnitude bits in two's complement code to sign-magnitude code, where n is an integer, comprising: coupling means for directly outputting a least significant bit and the sign bit of the binary number in two's complement code; and a rank ordered plurality of logic gates for providing a plurality of rank ordered magnitude bit by outputting the remainder of said n-1 magnitude bits if said binary number is positive, and otherwise identifying the least significant bit of said n-1 magnitude bits having a logic one value and inverting only the remainder of said n-1 magnitude bits of higher significance before outputting the remainder of said n-1 magnitude bits, each of said plurality of logic gates comprising: first logic means having a first input coupled to a carry in signal indicative of the logic state of the magnitude bit of next lower significance, a second input coupled to a respective one of the n-1 magnitude bits of said binary number, and an output; second logic means having a first input coupled to the output of the first logic means, a second input coupled to the sign bit of the n-bit number, and an output; and third logic means having a first input coupled to the output of the second logic means, a second input coupled to the magnitude bit of next higher significance than the magnitude bit which the second input of the first logic means is coupled to, and an output, for providing a predetermined bit of the binary number in sign-magnitude code.
Claim 2
Dependent Claim
268 words
A code conversion circuit, for converting an n-bit binary number having a sign bit and n-1 magnitude bits in two's complement code to sign-magnitude code, where n is an integer, comprising: coupling means for directly outputting a least significant bit and the sign bit of the binary number in two's complement code; and a rank ordered plurality of logic gates for providing a plurality of rank ordered magnitude bit by outputting the remainder of said n-1 magnitude bits if said binary number is positive, and otherwise identifying the least significant bit of said n-1 magnitude bits having a logic one value and inverting only the remainder of said n-1 magnitude bits of higher significance before outputting the remainder of said n-1 magnitude bits, each of said plurality of logic gates comprising: first logic means having a first input coupled to a carry in signal indicative of the logic state of the magnitude bit of next lower significance, a second input coupled to a respective one of the n-1 magnitude bits of said binary number, and an output; second logic means having a first input coupled to the output of the first logic means, a second input coupled to the sign bit of the n-bit number, and an output; and third logic means having a first input coupled to the output of the second logic means, a second input coupled to the magnitude bit of next higher significance than the magnitude bit which the second input of the first logic means is coupled to, and an output, for providing a predetermined bit of the binary number in sign-magnitude code.
Claim 3
Dependent Claim
35 words
The code conversion circuit of claim 1 wherein said plurality of logic gates convert said n-bit binary number from two's complement code to sign-magnitude code within one cycle of a clock signal of predetermined frequency.
Claim 4
Dependent Claim
34 words
The code conversion circuit of claim 1 further comprising: input means coupled to said logic means for receiving the sign bit and n-1 magnitude bits of said n-bit binary number in two's complement code.
Claim 5
Dependent Claim
32 words
The code conversion circuit of claim 3 further comprising: output means coupled to both said input means and said plurality of logic gates, for storing said n-bit binary number in sign-magnitude code.
Claim 6
Dependent Claim
256 words
A circuit for converting an n-bit binary number having a sign bit and n-1 magnitude bits in a two's complement code to sign-magnitude code, where n is an integer, comprising: a rank ordered plurality of logic gates, the first of said logic gates providing a second least significant magnitude bit in sign-magnitude code, the last of said logic gates providing a most significant magnitude bit in sign-magnitude code, and each of the remainder of said logic gates providing a magnitude bit of predetermined significance in sign-magnitude code, each of said logic gates comprising: first logic means having a first input coupled to a carry in signal indicative of the logic state of the magnitude bits of lower significance, a second input coupled to a respective one of the n-1 magnitude bits of said binary number, and an output; second logic means having a first input coupled to the output of said first logic means, a second input coupled to the sign bit of said binary number and an output; and third logic means having a first input coupled to the output of said second logic means, a second input coupled to the magnitude bit of next higher significance than the magnitude bit which the second input of said first logic means is coupled to, and an output, for providing a predetermined bit of the binary number in sign-magnitude code; and coupling means for directly coupling the least significant bit and the sign bit of the binary number in two's complement code to a respective output terminal.
Claim 7
Dependent Claim
256 words
A circuit for converting an n-bit binary number having a sign bit and n-1 magnitude bits in a two's complement code to sign-magnitude code, where n is an integer, comprising: a rank ordered plurality of logic gates, the first of said logic gates providing a second least significant magnitude bit in sign-magnitude code, the last of said logic gates providing a most significant magnitude bit in sign-magnitude code, and each of the remainder of said logic gates providing a magnitude bit of predetermined significance in sign-magnitude code, each of said logic gates comprising: first logic means having a first input coupled to a carry in signal indicative of the logic state of the magnitude bits of lower significance, a second input coupled to a respective one of the n-1 magnitude bits of said binary number, and an output; second logic means having a first input coupled to the output of said first logic means, a second input coupled to the sign bit of said binary number and an output; and third logic means having a first input coupled to the output of said second logic means, a second input coupled to the magnitude bit of next higher significance than the magnitude bit which the second input of said first logic means is coupled to, and an output, for providing a predetermined bit of the binary number in sign-magnitude code; and coupling means for directly coupling the least significant bit and the sign bit of the binary number in two's complement code to a respective output terminal.
Claim 8
Dependent Claim
31 words
The circuit of claim 5 wherein said logic gates convert said n-bit binary number from two's complement code to sign-magnitude code within one cycle of a clock signal of predetermined frequency.
Claim 9
Dependent Claim
39 words
The circuit of claim 5 further comprising: input means coupled to both said rank ordered plurality of logic gates and coupling means, for receiving the sign bit and n-1 magnitude bits of said binary number in two's complement code.
Claim 10
Dependent Claim
32 words
The circuit of claim 5 further comprising: output means coupled to both said rank ordered plurality of logic gates and said coupling means, for storing said n-bit binary number in sign-magnitude code.
References Cited (Backward Citations)
US4087754A
Cited
US3949299A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-05-27 | 1988-11-26 | 1989-05-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-05-27 | 1992-11-26 | 1993-05-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-05-27 | 1996-11-26 | 1997-05-28 | $7700.00 | Window Closed / Lapsed |