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US4518926A
Expired / Lapsed
US
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Gate-coupled field-effect transistor pair amplifier
Assignee: Nokia Bell Labs
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Filing: 1982-12-20
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Granted: 1985-05-21
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Expires: 2002-12-20
Abstract
Abstract An enhancement mode (104, 204, 404) and a depletion mode (102, 202, 402) pair of N-channel MOS transistors have their drain-source conduction paths connected in series and provided with a bias current means (120, 220, 306, 410). The gates (106, 206, 308, 310) are coupled together as an input node. In one embodiment (100) their bulk regions are source-connected and the output (118) is from the source of the enhancement mode device (104) to obtain a source follower configuration amplifier. In a second embodiment (200), the output (218) is taken from the drain (208) of the depletion mode device (202) to obtain a common source configuration amplifier. Two source follower pairs (302, 304) are disclosed connected in parallel to form a differential input voltage amplifier stage (300). A common source pair (402, 404) is disclosed in combination with an additional enhancement mode transistor (406) to form a current mirror (400).
Inventors
- 👤 Eric J. Swanson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 15:22
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/50; H03F3/505; H03F3/34; H03F3/343; H03F3/345
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
50 words
The combination of a first enhancement mode and a first depletion mode field effect transistor with their gates connected together and providing a linear input node, their drain-to-source conduction paths being connected in series and provided with a substantially constant bias current supply means for establishing a bias current therethrough.
Claim 2
Dependent Claim
50 words
The combination of a first enhancement mode and a first depletion mode field effect transistor with their gates connected together and providing a linear input node, their drain-to-source conduction paths being connected in series and provided with a substantially constant bias current supply means for establishing a bias current therethrough.
Claim 3
Dependent Claim
14 words
The combination of claim 1 wherein said transistors have the same conducting channel polarity.
Claim 4
Dependent Claim
68 words
The combination of claim 2 wherein the drain of said depletion mode transistor is connected to a first polarity supply voltage means and the source of said enhancement mode transistor is connected in series with the bias current supply means to a second polarity supply voltage means, the gates providing an input node and the source of said enhancement mode transistor providing a substantially unity gain output node.
Claim 5
Dependent Claim
67 words
The combination of claim 2 wherein the source of said enhancement mode transistor is connected to a first polarity supply voltage means and the drain of said depletion mode transistor is connected in series with the bias current supply means to a second polarity supply voltage means, the gates providing an input node and the drain of said depletion mode transistor providing a voltage amplified output node.
Claim 6
Dependent Claim
105 words
The combination of claim 2 comprising a second enhancement mode and a second depletion mode field effect transistor with their gates coupled together and their drain-source conduction paths connected in series with each other and in parallel with those of said first transistors to form a common node of said first and second enhancement transistors, said common node being connected in series with the bias current supply means to a power supply voltage means, the gates of said first transistors and said second transistors providing differential input nodes and the drains of said first and second depletion mode transistors providing respective differential current output nodes.
Claim 7
Dependent Claim
83 words
The combination of claim 1 comprising a second enhancement mode transistor having its gate and its drain coupled to the gate of said first transistors and connected in series with the bias current supply means to an input current node, the source of said first and second enhancement mode transistors being connected together to a first polarity supply voltage means, the drain of said first depletion mode transistor forming an output current node with a current mirror relationship to said input current node.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-05-20 | 1988-11-19 | 1989-05-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-05-20 | 1992-11-19 | 1993-05-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-05-20 | 1996-11-19 | 1997-05-21 | $7700.00 | Window Closed / Lapsed |