US4518925A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Signal processing circuits
Assignee: Sony Corp
•
Filing: 1983-12-29
•
Granted: 1985-05-21
•
Expires: 2003-12-29
Abstract
Abstract A signal processing circuit comprises an amplifying circuit portion having an input terminal connected to a signal source, an output terminal for delivering an amplifier signal therefrom and a control terminal, a capacitive device coupled to the control terminal for serving as a bypass capacitor for the amplifying circuit portion, a charging circuit portion connected to the control terminal for forming a path for a charging current to the capacitive device, a discharging circuit portion also connected to the control terminal for forming a path for a discharging current from the capacitive device, and a control circuit portion having a terminal supplied with a control signal taking at least first and second states and being operative to control both the charging and discharging circuit portions. The control circuit portion controls the charging circuit portion to allow the charging current to flow to the capacitive device so as to produce thereat a potential for making the amplifying circuit portion inoperative when the control signal is turned to take the first state and also control the discharging circuit portion to allow the discharging current to flow from the capacitive device so as to produce a potential thereat for making the amplifying circuit portion operative when the control signal is turned to take the second state.
Inventors
- 👤 Hideki Fukasawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 20:26
CPC Classifications
G; G11; G11B; G11B15/00; G11B15/02; G11B15/12; G11B15/14; G11B5/00; G11B5/48; G11B5/58; G11B5/584; G11B5/588; G11B5/592; G11B5/5921; G11B5/5922; H; H03; H03F; H03F3/00; H03F3/72
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
220 words
A signal processing circuit for supplying with an amplified output signal, comprising; amplifying circuit means having an input terminal connected to a signal source, an output terminal for delivering the amplified output signal threrfrom, and a control terminal, capacitive means coupled to the control terminal of said amplifying circuit means for serving as a bypass capacitor for said amplifying circuit means, charging circuit means connected to the control terminal of said amplifying circuit means for forming a path for a charging current to said capacitive means, discharging circuit means connected to the control terminal of said amplifying circuit means for forming a path for a discharging current from said capacitive means, and controlling circuit means having a control signal input terminal supplied with a control signal taking at least first and second states, and being operative to control said charging circuit means to allow the charging current to flow to said capacitive means so as to produce thereat a potential for making said amplifying circuit means inoperative when said control signal is turned to take the first state and control said discharging circuit means to allow the discharging current to flow from said capacitive means to as to produce thereat a potential for making said amplifying circuit means operative when the control signal is turned to take the second state.
Claim 2
Dependent Claim
220 words
A signal processing circuit for supplying with an amplified output signal, comprising; amplifying circuit means having an input terminal connected to a signal source, an output terminal for delivering the amplified output signal threrfrom, and a control terminal, capacitive means coupled to the control terminal of said amplifying circuit means for serving as a bypass capacitor for said amplifying circuit means, charging circuit means connected to the control terminal of said amplifying circuit means for forming a path for a charging current to said capacitive means, discharging circuit means connected to the control terminal of said amplifying circuit means for forming a path for a discharging current from said capacitive means, and controlling circuit means having a control signal input terminal supplied with a control signal taking at least first and second states, and being operative to control said charging circuit means to allow the charging current to flow to said capacitive means so as to produce thereat a potential for making said amplifying circuit means inoperative when said control signal is turned to take the first state and control said discharging circuit means to allow the discharging current to flow from said capacitive means to as to produce thereat a potential for making said amplifying circuit means operative when the control signal is turned to take the second state.
Claim 3
Dependent Claim
33 words
A signal processing circuit according to claim 1, wherein said controlling circuit means comprises first control means for controlling said charging circuit means and second control means for controlling said discharging circuit means.
Claim 4
Dependent Claim
57 words
A signal processing circuit according to claim 2, wherein said second control means includes a comparator for comparing a variable potential obtained in response to a potential at the control terminal of said amplifying circuit means with a reference potential and producing an output of a result of the comparision to control therewith said discharging circuit means.
Claim 5
Dependent Claim
23 words
A signal processing circuit according to claim 3, wherein said variable potential is derived from the output terminal of said amplifying circuit means.
Claim 6
Dependent Claim
47 words
A signal processing circuit according to claim 1, wherein said amplifying circuit means includes an amplifying transistor having a base connected to the input terminal and an emitter connected to the control terminal, and said capacitive means comprises a capacitor connected to the emitter of said transistor.
Claim 7
Dependent Claim
32 words
A signal processing circuit according to claim 5, wherein said amplifying circuit means further includes at least one additional transistor connected between a collector of said amplifying transistor and the output terminal.
Claim 8
Dependent Claim
28 words
A signal processing circuit according to claim 1, wherein said signal source comprises transducer means employed in recording and reproducing apparatus from which a reproduced signal is supplied.
Claim 9
Dependent Claim
47 words
A signal processing circuit according to claim 7, said control signal supplied to the control signal input terminal of said controlling circuit means takes the first and second states selectively in response to the recording mode and the reproducing mode in said recording and reproducing apparatus, respectively.
References Cited (Backward Citations)
US4435684A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-05-20 | 1988-11-19 | 1989-05-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-05-20 | 1992-11-19 | 1993-05-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-05-20 | 1996-11-19 | 1997-05-21 | $7700.00 | Window Closed / Lapsed |