Patent US4517657A successfully refreshed from Google Patents.
US4517657A
Expired / Lapsed
US
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Integrated bit processor/word processor control system
Assignee: Dr Johannes Heidenhain GmbH
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Filing: 1982-07-13
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Granted: 1985-05-14
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Expires: 2002-07-13
Abstract
Abstract A freely programmable control system is disclosed which includes a computer, a data memory, and a program memory, as well as a program controllable logical network for individual bit processing and an individual bit memory. The disclosed control system operates as an integrated system which utilizes both commands for the computer and separate commands for individual bit processing. Both types of commands are stored in the program memory as an integrated program. During individual bit processing the commands for the individual bit operations are routed from the program memory to the logical network circuit for individual bit processing, and are there executed. Similarly, during computer processing the commands for the computer are transferred directly to the computer and are there executed. The commands for the individual bit processing are kept away from the computer by a switching circuit which operates to supply the computer with a command to increment the computer program counter for each individual bit instruction.
Inventors
- 👤 Ernst Schwefel
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 14:16
CPC Classifications
G; G05; G05B; G05B19/00; G05B19/02; G05B19/04; G05B19/05; G05B19/052; G05B2219/00; G05B2219/10; G05B2219/15; G05B2219/15127
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
265 words
In a programmable process control system of the type comprising a multiple bit computer which comprises a program counter, a data memory coupled to the computer, and a program memory which stores a plurality of computer commands, the improvement comprising: a program controllable logical network comprising means for providing individual bit processing of individual bit information; a bit memory coupled to the logical network for storing said individual bit information; a plurality of commands for the bit processing means stored in the program memory, said computer commands and said commands for the bit processing means stored in the program memory as an integrated program for the process control system; and means for interconnecting the program memory, the computer, and the logical network to form an integrated process control system, said interconnecting means comprising: first means, responsive to the program counter, for directing the plurality of commands for the bit processing means from the program memory to the logical network for execution by the bit processing means; second means, responsive to the program counter, for directing the plurality of computer commands from the program memory to the computer for execution by the computer; switching means for isolating the computer from the plurality of commands for the bit processing means; and means for supplying to the computer a computer command for incrementing the program counter in response to each of the plurality of commands for the bit processing means from which the computer is isolated, such that the command reading time of the computer is preserved during the execution of commands by the individual bit processing means.
Claim 2
Dependent Claim
265 words
In a programmable process control system of the type comprising a multiple bit computer which comprises a program counter, a data memory coupled to the computer, and a program memory which stores a plurality of computer commands, the improvement comprising: a program controllable logical network comprising means for providing individual bit processing of individual bit information; a bit memory coupled to the logical network for storing said individual bit information; a plurality of commands for the bit processing means stored in the program memory, said computer commands and said commands for the bit processing means stored in the program memory as an integrated program for the process control system; and means for interconnecting the program memory, the computer, and the logical network to form an integrated process control system, said interconnecting means comprising: first means, responsive to the program counter, for directing the plurality of commands for the bit processing means from the program memory to the logical network for execution by the bit processing means; second means, responsive to the program counter, for directing the plurality of computer commands from the program memory to the computer for execution by the computer; switching means for isolating the computer from the plurality of commands for the bit processing means; and means for supplying to the computer a computer command for incrementing the program counter in response to each of the plurality of commands for the bit processing means from which the computer is isolated, such that the command reading time of the computer is preserved during the execution of commands by the individual bit processing means.
Claim 3
Dependent Claim
56 words
The invention of claim 1 wherein the interconnecting means further comprises: means for activating the first means to direct commands to the bit processing means in response to a predetermined computer command; and means for activating the second means to direct commands to the computer in response to a predetermined command for the bit processing means.
Claim 4
Dependent Claim
21 words
The invention of claim 1 wherein the first and second means are activated by respective selected addresses of the program memory.
Claim 5
Dependent Claim
82 words
The invention of claim 1 further comprising: an input unit coupled to the bit memory to modify a first set of preselected bit storage devices included in the bit memory to correspond to measured variables; an output unit coupled to the bit memory to interface with a second set of preselected bit storage devices included in the bit memory; and means for synchronizing the transfer of information between the bit memory and the input unit and the output unit with the computer.
Claim 6
Dependent Claim
39 words
The invention of claim 1 further comprising: means for interconnecting the bit memory and the logical network when the first means is activated; and means for interconnecting the bit memory and the computer when the second means is activated.
Claim 7
Dependent Claim
24 words
The invention of claim 1 wherein the switching means comprises means for connecting the computer with both the logical network and the program memory.
Claim 8
Dependent Claim
40 words
The invention of claim 1 wherein the logical network is separate from the computer, and wherein the logical network comprises means for executing a set of individual bit logical operations on pairs of bit information stored in the bit memory.
Claim 9
Dependent Claim
17 words
The invention of claim 7 wherein the set of individual logical bit operations comprises the AND operation.
Claim 10
Dependent Claim
23 words
The invention of claim 7 wherein the set of individual logical bit operations comprises the AND, NAND, OR, NOR, XOR, and XNOR operations.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-05-13 | 1988-11-12 | 1989-05-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-05-13 | 1992-11-12 | 1993-05-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-05-13 | 1996-11-12 | 1997-05-14 | $7700.00 | Window Closed / Lapsed |