Dual peak detector

Claim 2

A dual peak detector circuit comprising: a first circuit means for receiving an input voltage and storing the maximum value of said input voltage; a second circuit means for receiving said input voltage and storing the minimum value of said input voltage; and a third circuit means connected to said first and said second circuit means, said third circuit means for providing an output when said input voltage transitions from said maximum value to said minimum value by storing a selected portion of the voltage difference between said maximum voltage and said minimum voltage and providing said output when said input voltage is less than the sum of the selected portion and the minimum voltage.

Claim 3

A dual peak detector according to claim 1 wherein first circuit means includes a capacitor connected to a diode, said diode connected to permit the charging of said capacitor and prevent the discharging of said capacitor when said input voltage decreases from the voltage stored in said capacitor.

Claim 4

A dual peak detector circuit according to claim 2, wherein said first circuit means includes an operational amplifier that is connected to said input voltage, said diode and said capacitor for charging said capacitor to said maximum input voltage value.

Claim 5

A dual peak detector circuit according to claim 3, wherein second circuit means includes a second diode and second capacitor connected to allow the second capacitor to charge to the minimum input voltage value and to discharge any voltage above the minimum value through the second diode.

Claim 6

A dual peak detector circuit according to claim 4, wherein second circuit means includes an operational amplifier connected to said second diode.

Claim 7

A dual peak detector according to claim 5, wherein said third circuit means includes a third capacitor and a resistor voltage divider connected such that said third capacitor stores the difference between said maximum input voltage and said minimum input voltage and said voltage divider outputs a selected portion of said difference voltage to a comparator which provides said output from said third circuit means.

Claim 8

A dual peak detector according to claim 6, wherein third circuit means further includes a first and second buffer connected on either side on said third capacitor to buffer the third capacitor from said voltage divider.

Claim 9

A dual peak detector according to claim 7, wherein said third circuit means further includes a fourth capacitor that is connected between the output of the comparator and one of the inputs to the comparator to reduce noise.

Claim 10

A bar code optical reader circuit comprising: an optical bar code sensing circuit including a light-emitting diode means for emitting light and a photosensitive transistor means for receiving light from said light-emitting diode means that has been reflected from a surface and providing a voltage input; a first circuit means for receiving said voltage input and storing the maximum value of said voltage input; a second circuit means for receiving said voltage input and for storing the minimum value of said voltage input; and a third circuit means connected to said voltage input and said first and said second circuit means, said third circuit means for providing an output when said input voltage transitions from said maximum value to said minimum value by storing a selected portion of voltage difference between the maximum input voltage and the minimum input voltage and providing said output when said input voltage is less than the sum of the selected portion of the voltage difference and said minimum input voltage.

Claim 11

A bar code optical reader circuit comprising: an optical bar code sensing circuit including a light-emitting diode means for emitting light and a photosensitive transistor means for receiving light from said light-emitting diode means that has been reflected from a surface and providing a voltage input; a first circuit means for receiving said voltage input and storing the maximum value of said voltage input; a second circuit means for receiving said voltage input and for storing the minimum value of said voltage input; and a third circuit means connected to said voltage input and said first and said second circuit means, said third circuit means for providing an output when said input voltage transitions from said maximum value to said minimum value by storing a selected portion of voltage difference between the maximum input voltage and the minimum input voltage and providing said output when said input voltage is less than the sum of the selected portion of the voltage difference and said minimum input voltage.