Patent US4516219A successfully refreshed from Google Patents.
US4516219A
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Address designating method of memory and apparatus therefor
Assignee: Mitsubishi Electric Corp
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Filing: 1982-12-02
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Granted: 1985-05-07
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Expires: 2002-12-02
Abstract
Abstract An address designating method of a memory is performed by dividing the addresses of the memory to row addresses and column addresses. The writing of data in the memory is performed by the following steps. Namely, while the row addressing is maintained in a predetermined value (for example, 7d+1), the column addressing is incremented one by one. When the column addressing reaches 3, the row addressing is decremented by 4d+1. Each time the row addressing is decremented by d, the column addressing is decremented one by one in accord therewith. The reading of the data from the memory is performed by the following steps. Namely, each time the row addressing is incremented by d, the column addressing is also incremented one by one in accord therewith. When the column addressing reaches 3, the row addressing is decremented by 3d+1. With the row addressing kept in 0, the column addressing is decremented one by one.
Inventors
- 👤 Masayuki Ishida
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 00:54
CPC Classifications
G; G11; G11B; G11B27/00; G11B27/10; G11B27/102; G11B20/00; G11B20/10; G11B20/18; G11B20/1806; G11B20/1809
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
225 words
A method of designating addresses of a memory by dividing the addresses of the memory into row addresses of row addressing and column addresses of column addressing, said method comprising the steps of, on the occasion of the writing of the data in said memory, adding a predetermined integer value B in succession to said column addressing by maintaining said row addressing in a predetermined positive integer value A, subtracting a predetermined integer value D from said row addressing responsive to reaching of said column addressing to a predetermined positive integer value C, and subtracting in succession a predetermined integer value B from said row addressing while subtracting said predetermined integer value B in succession from said column addressing in accord therewith, and on the occasion of the reading of the data from said memory, adding said predetermined integer value E in succession to said row addressing obtained by subtracting a predetermined integer value F from said predetermined integer value A, while adding said predetermined integer value B in succession to said column addressing in accord therewith, subtracting a predetermined integer value G from said row addressing responsive to reaching of said column addressing to said predetermined integer value C, and subtracting said predetermined integer value B in succession from said column addressing by maintaining said row addressing in a predetermined positive integer value H.
Claim 2
Independent Claim
225 words
A method of designating addresses of a memory by dividing the addresses of the memory into row addresses of row addressing and column addresses of column addressing, said method comprising the steps of, on the occasion of the writing of the data in said memory, adding a predetermined integer value B in succession to said column addressing by maintaining said row addressing in a predetermined positive integer value A, subtracting a predetermined integer value D from said row addressing responsive to reaching of said column addressing to a predetermined positive integer value C, and subtracting in succession a predetermined integer value B from said row addressing while subtracting said predetermined integer value B in succession from said column addressing in accord therewith, and on the occasion of the reading of the data from said memory, adding said predetermined integer value E in succession to said row addressing obtained by subtracting a predetermined integer value F from said predetermined integer value A, while adding said predetermined integer value B in succession to said column addressing in accord therewith, subtracting a predetermined integer value G from said row addressing responsive to reaching of said column addressing to said predetermined integer value C, and subtracting said predetermined integer value B in succession from said column addressing by maintaining said row addressing in a predetermined positive integer value H.
Claim 3
Dependent Claim
28 words
An address designating method of a memory in accordance with claim 1, wherein said predetermined integer values B, D, E, F and G are each a positive value.
Claim 4
Dependent Claim
37 words
An address designating method of a memory in accordance with claim 1, wherein said predetermined integer values D, E, F and G are each a positive value, and said predetermined integer value B is a negative value.
Claim 5
Dependent Claim
39 words
An address designating method of a memory in accordance with claim 1, wherein said predetermined integer values E and F are each a positive value, and said predetermined integer values B, D and G are each a negative value.
Claim 6
Dependent Claim
39 words
An address designating method of a memory in accordance with claim 1, wherein said predetermined integer values B, E and F are each a positive value, and said predetermined integer values D and G are each a negative value.
Claim 7
Dependent Claim
43 words
An address designating method of a memory in accordance with claim 1, wherein said predetermined integer values B, D and G are each a positive value, said predetermined integer value E is a negative value, and said predetermined integer value F is zero.
Claim 8
Dependent Claim
45 words
An address designating method of a memory in accordance with claim 1, wherein said predetermined integer values D and G are each a positive value, said predetermined integer values B and E are each a negative value, and said predetermined integer value F is zero.
Claim 9
Dependent Claim
37 words
An address designating method of a memory in accordance with claim 1, wherein said predetermined integer value F is a positive value, and said predetermined integer values B, D, E and G are each a negative value.
Claim 10
Dependent Claim
39 words
An address designating method of a memory in accordance with claim 1, wherein said predetermined integer values B and F are each a positive value, and said predetermined integer values D, E and G are each a negative value.
Claim 11
Independent Claim
347 words
An apparatus for designating addresses of a memory having row addresses of row addressing and column addresses of column addressing, comprising: write address designating means (20) for designating the addresses on the occasion of the writing of the data in said memory, said write address designating means (20) comprising first address designating means (21 to 23) for adding in succession a predetermined integer value B to said column addressing by maintaining said row addressing in a predetermined integer value A, second address designating means (27) responsive to reaching of said column addressing to a predetermined positive integer value C for subtracting a predetermined integer value D from said row addressing, and third address designating means (21 to 26) for subtracting in succession a predetermined integer value E from said row addressing while subtracting in succession said predetermined integer value B from said column addressing in accord therewith, initial setting means (50) coupled to said write address designating means (20) for subtracting a predetermined integer value F from said predetermined integer value A, thereby to provide an initial read row address, read address designating means (30) coupled to said initial setting means (50) for designating the addresses on the occasion of reading the data from said memory, said read address designating means (30) comprising fourth address designating means (31 to 36) for adding in succession said predetermined integer value E to said initial read row address while adding in succession said predetermined value B to said column addressing in accord wherewith, fifth address designating means (37) responsive to reaching of said column addressing to said predetermined integer value C for subtracting a predetermined integer value G from said row addressing, and sixth address designating means (31 to 33) for subtracting in succession said predetermined integer value B from said column addressing while maintaining said row addressing in a predetermined integer value H, and selector means (14) coupled to said write address designating means (20) and said read address designating means (30) for selecting either of said write address designating means (20) and said read address designating means (30).
Claim 12
Independent Claim
347 words
An apparatus for designating addresses of a memory having row addresses of row addressing and column addresses of column addressing, comprising: write address designating means (20) for designating the addresses on the occasion of the writing of the data in said memory, said write address designating means (20) comprising first address designating means (21 to 23) for adding in succession a predetermined integer value B to said column addressing by maintaining said row addressing in a predetermined integer value A, second address designating means (27) responsive to reaching of said column addressing to a predetermined positive integer value C for subtracting a predetermined integer value D from said row addressing, and third address designating means (21 to 26) for subtracting in succession a predetermined integer value E from said row addressing while subtracting in succession said predetermined integer value B from said column addressing in accord therewith, initial setting means (50) coupled to said write address designating means (20) for subtracting a predetermined integer value F from said predetermined integer value A, thereby to provide an initial read row address, read address designating means (30) coupled to said initial setting means (50) for designating the addresses on the occasion of reading the data from said memory, said read address designating means (30) comprising fourth address designating means (31 to 36) for adding in succession said predetermined integer value E to said initial read row address while adding in succession said predetermined value B to said column addressing in accord wherewith, fifth address designating means (37) responsive to reaching of said column addressing to said predetermined integer value C for subtracting a predetermined integer value G from said row addressing, and sixth address designating means (31 to 33) for subtracting in succession said predetermined integer value B from said column addressing while maintaining said row addressing in a predetermined integer value H, and selector means (14) coupled to said write address designating means (20) and said read address designating means (30) for selecting either of said write address designating means (20) and said read address designating means (30).
Claim 13
Dependent Claim
28 words
An address designating apparatus of a memory in accordance with claim 10, wherein said predetermined integer values B, D, E, F and G are each a positive value.
Claim 14
Dependent Claim
37 words
An address designating apparatus of a memory in accordance with claim 10, wherein said predetermined integer values D, E, F, and G are each a positive value, and said predetermined integer value B is a negative value.
Claim 15
Dependent Claim
39 words
An address designating apparatus of a memory in accordance with claim 10, wherein said predetermined integer values E and F are each a positive value, and said predetermined integer value B, D and G are each a negative value.
Claim 16
Dependent Claim
39 words
An address designating apparatus of a memory in accordance with claim 10, wherein said predetermined integer values B, E and F are each a positive value, and said predetermined integer values D and G are each a negative value.
Claim 17
Dependent Claim
40 words
An address designating apparatus in accordance with claim 10, wherein said predetermined integer values B, D, and G are each a positive value, said predetermined integer value E is a negative value, and said predetermined integer value F is zero.
Claim 18
Dependent Claim
42 words
An address designating apparatus in accordance with claim 10, wherein said predetermined integer values D and G are each a positive value, said predetermined integer value B and E are each a negative value, and said predetermined integer value F is zero.
Claim 19
Dependent Claim
37 words
An address designating apparatus of a memory in accordance with claim 10, wherein said predetermined integer value F is a positive value, and said predetermined integer values B, D, E and G are each a negative value.
Claim 20
Dependent Claim
36 words
An address designating apparatus in accordance with claim 10, wherein said predetermined integer values B and F are each a positive value, and said predetermined integer values D, E and G are each a negative value.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-05-06 | 1988-11-05 | 1989-05-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-05-06 | 1992-11-05 | 1993-05-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-05-06 | 1996-11-05 | 1997-05-07 | $7700.00 | Window Closed / Lapsed |