Patent US4516163A successfully refreshed from Google Patents.
US4516163A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Digital information signal recording system
Assignee: VICTO Co OF JAPAN Ltd
•
Filing: 1983-06-28
•
Granted: 1985-05-07
•
Expires: 2003-06-28
Abstract
Abstract A digital information recording system comprises a randomized digital signal forming circuit for forming a randomized digital signal by carrying out modulo-2 addition of at least digital information signals of a plurality of channels in a digital signal and a random code sequence which is generated independently, a detector for successively detecting values of each of a predetermined number of words from each of the digital information signals of a plurality of channels in the randomized digital signal, in terms of one word, and generating a detection signal only when values of bits in the one word are all "1" or all "0", a timing circuit for generating a timing signal for every period corresponding to a transmission period of a least significant bit in one word from each of the digital information signals of a plurality of channels, a polarity inverting circuit for passing the randomized digital signal unchanged during a period in which the detection signal is not generated from the detector, and inverting the polarity of the least significant bit in one word from each of the digital information signals of a plurality of channels in the randomized digital signal when simultaneously applied with the detection signal and the timing signal, and a recording circuit for recording a digital signal obtained from the polarity inverting circuit.
Inventors
- 👤 Isao Masuda
- 👤 Nobuaki Takahashi
- 👤 Kazunori Nishikawa
- 👤 Yoshiki Iwasaki
- 👤 Shoji Ueno
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 18:12
CPC Classifications
G; G11; G11B; G11B20/00; G11B20/10; G11B20/18; G11B20/1806; G11B20/1809; G11B20/10527
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
290 words
A digital information recording system comprising: a randomized digital signal forming circuit for forming a randomized digital signal by carrying out modulo-2 addition of at least digital information signals of a plurality of channels in a digital signal and a random code sequence which is generated independently, said digital signal being constituted by a predetermined number of words from each of said digital information signals of a plurality of channels, a synchronizing signal, error correcting codes, and an error detecting code, which are time-sequentially multiplexed in terms of signals corresponding to one frame, said digital information signals of a plurality of channels being obtained by independently subjecting analog information signals of a plurality of channels to digital modulation; a detector for successively detecting values of each of said predetermined number of words from each of said digital information signals of a plurality of channels in said randomized digital signal, in terms of one word, and generating a detection signal only when values of bits in said one word are all "1" or all "0"; a timing circuit for generating a timing signal for every period corresponding to a transmission period of a least significant bit in one word from each of said digital information signals of a plurality of channels; polarity inverting circuit means for passing said randomized digital signal unchanged during a period in which said detection signal is not generated from said detector, and inverting the polarity of the least significant bit in one word from each of said digital information signals of a plurality of channels in said randomized digital signal when simultaneously applied with said detection signal and said timing signal; and recording means for recording a digital signal obtained from said polarity inverting circuit means.
Claim 2
Dependent Claim
290 words
A digital information recording system comprising: a randomized digital signal forming circuit for forming a randomized digital signal by carrying out modulo-2 addition of at least digital information signals of a plurality of channels in a digital signal and a random code sequence which is generated independently, said digital signal being constituted by a predetermined number of words from each of said digital information signals of a plurality of channels, a synchronizing signal, error correcting codes, and an error detecting code, which are time-sequentially multiplexed in terms of signals corresponding to one frame, said digital information signals of a plurality of channels being obtained by independently subjecting analog information signals of a plurality of channels to digital modulation; a detector for successively detecting values of each of said predetermined number of words from each of said digital information signals of a plurality of channels in said randomized digital signal, in terms of one word, and generating a detection signal only when values of bits in said one word are all "1" or all "0"; a timing circuit for generating a timing signal for every period corresponding to a transmission period of a least significant bit in one word from each of said digital information signals of a plurality of channels; polarity inverting circuit means for passing said randomized digital signal unchanged during a period in which said detection signal is not generated from said detector, and inverting the polarity of the least significant bit in one word from each of said digital information signals of a plurality of channels in said randomized digital signal when simultaneously applied with said detection signal and said timing signal; and recording means for recording a digital signal obtained from said polarity inverting circuit means.
Claim 3
Dependent Claim
38 words
A digital information signal recording system as claimed in claim 1 in which said digital information signals, the values of which are detected by said detector, are digital audio data obtained by subjecting audio signals to digital modulation.
Claim 4
Dependent Claim
99 words
A digital information signal recording system as claimed in claim 1 in which said detector comprises a shift register supplied with said randomized digital signal from said randomized digital signal forming circuit, for subjecting a signal having bits corresponding to one word from each of said digital information signals of a plurality of channels to series-to-parallel conversion; an AND circuit supplied with a parallel output signal of said shift register; a NOR circuit supplied with the parallel output signal of said shift register; and an OR circuit supplied with output signals of said AND circuit and said NOR circuit.
Claim 5
Dependent Claim
59 words
A digital information signal recording system as claimed in claim 1 in which said polarity inverting circuit means comprises an AND circuit supplied with the output signal of said detector and said timing signal, and an exclusive-OR circuit supplied with an output signal of said AND circuit and said randomized digital signal from said randomized digital signal forming circuit.
Claim 6
Dependent Claim
41 words
A digital information signal recording system as claimed in claim 1 in which said error detecting code is generated according to said digital information signals of a plurality of channels in said digital signal obtained from said polarity inverting circuit means.
Claim 7
Dependent Claim
87 words
A digital information signal recording system as claimed in claim 4 in which said randomized digital signal from said randomized digital signal forming circuit is a signal produced in series from a least significant bit terminal of a shift register, said shift register being supplied with said randomized digital signal from said randomized digital signal forming circuit and subjecting a signal having bits corresponding to one word from each of said digital information signals of a plurality of channels in said randomized digital signal to series-to-parallel conversion.
References Cited (Backward Citations)
US4467373A
Cited
US4466089A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-05-06 | 1988-11-05 | 1989-05-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-05-06 | 1992-11-05 | 1993-05-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-05-06 | 1996-11-05 | 1997-05-07 | $7700.00 | Window Closed / Lapsed |