Patent US4514805A successfully refreshed from Google Patents.
US4514805A
Expired / Lapsed
US
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Interrupt operation in systems emulator mode for microcomputer
Assignee: Texas Instruments Inc
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Filing: 1982-02-22
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Granted: 1985-04-30
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Expires: 2002-02-22
Abstract
Abstract A system for real-time digital signal processing employs a single-chip microcomputer device having separate on-chip program ROM and data RAM, with separate address and data paths for program and data; however, the accumulator in the data path may be used as a program address source for table look-up for accumulator addressing, for example. An external program address bus allows off-chip program fetch in an expansion mode, with the opcode returned by an external data bus. The on-chip program memory may be disabled and only off-chip memory used for program fetch in a systems emulator mode. A non-maskable interrupt procedure used in the emulator mode generates a vector address for the on-chip ROM in switching between memory expansion and emulator modes, using an overvoltage detector to signal this condition.
Inventors
- 👤 Kevin C. McDonough
- 👤 Gary L. Swoboda
- 👤 Surendar S. Magar
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 14:20
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/36; G06F11/362; G06F11/3648; G06F9/00; G06F9/06; G06F9/22; G06F9/26; G06F9/262; G06F9/268
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
458 words
A microcomputer system comprising: a microcomputer device formed in a single integrated circuit and having data input/output terminals, address output terminals, a pair of voltage supply terminals receiving a supply voltage of a given level, and control terminals including a mode control terminal; the microcomputer device having an arithmetic/logic unit, a data memory, an internal program memory, and control means; the microcomputer device being operated by logic voltages on said data input/output terminals and said control terminals of about said given level; program memory means external to the microcomputer device having an address input operated by address voltages of about said given level and having data output means; input/output peripheral means for transfer of information to or from external equipment including application of selected voltages to said mode control terminal; said information being voltages of about said given level; said selected voltages being voltages of said given level and also an interrupt voltage at a level substantially above said given level; external address bus means coupled to the address output terminals of the microcomputer device and to the address input of the external program memory means; external data bus means coupled to the data input/output terminals of the microcomputer device and to the data output means of the external program memory means; said data memory having an address input and having data input/output means; said internal program memory having an address input and having an instruction output, the internal program memory storing instruction words; program address means within the microcomputer device connected to the address input of said internal program memory; said control means generating controls in response to instruction words, the controls defining operation of the arithmetic/logic unit and transfer to and from internal bus means; internal bus means coupled to the data input and data output of the arithmetic/logic unit, to the data input/output means of the data memory, to said instruction output of the internal program memory, to said control means, to said address output terminals, to said data input/output terminals, and to said program address means; mode switching means within the microcomputer device to apply program addresses either to said program address means of the internal program memory or to said address output terminals for transfer via said external address bus means to the external program memory means, the mode switching means being operated by voltages of said given level and not exceeding said given level on by the mode control terminal, and interrupt means coupled to the mode switching means and responsive to said interrupt voltage on the mode control terminal at said level substantially above said given level to cause a non-maskable interrupt wherein a fixed vector address is applied to said program address means and an existing program address is saved.
Claim 2
Dependent Claim
458 words
A microcomputer system comprising: a microcomputer device formed in a single integrated circuit and having data input/output terminals, address output terminals, a pair of voltage supply terminals receiving a supply voltage of a given level, and control terminals including a mode control terminal; the microcomputer device having an arithmetic/logic unit, a data memory, an internal program memory, and control means; the microcomputer device being operated by logic voltages on said data input/output terminals and said control terminals of about said given level; program memory means external to the microcomputer device having an address input operated by address voltages of about said given level and having data output means; input/output peripheral means for transfer of information to or from external equipment including application of selected voltages to said mode control terminal; said information being voltages of about said given level; said selected voltages being voltages of said given level and also an interrupt voltage at a level substantially above said given level; external address bus means coupled to the address output terminals of the microcomputer device and to the address input of the external program memory means; external data bus means coupled to the data input/output terminals of the microcomputer device and to the data output means of the external program memory means; said data memory having an address input and having data input/output means; said internal program memory having an address input and having an instruction output, the internal program memory storing instruction words; program address means within the microcomputer device connected to the address input of said internal program memory; said control means generating controls in response to instruction words, the controls defining operation of the arithmetic/logic unit and transfer to and from internal bus means; internal bus means coupled to the data input and data output of the arithmetic/logic unit, to the data input/output means of the data memory, to said instruction output of the internal program memory, to said control means, to said address output terminals, to said data input/output terminals, and to said program address means; mode switching means within the microcomputer device to apply program addresses either to said program address means of the internal program memory or to said address output terminals for transfer via said external address bus means to the external program memory means, the mode switching means being operated by voltages of said given level and not exceeding said given level on by the mode control terminal, and interrupt means coupled to the mode switching means and responsive to said interrupt voltage on the mode control terminal at said level substantially above said given level to cause a non-maskable interrupt wherein a fixed vector address is applied to said program address means and an existing program address is saved.
Claim 3
Dependent Claim
59 words
A system according to claim 1 including timing means for establishing an operating cycle during which data may be transferred from the data memory to the data input of the arithmetic/logic unit, the program address means applies an address to the address input of the program memory, and the control means receives an instruction word from the instruction output.
Claim 4
Dependent Claim
12 words
A system according to claim 2 wherein successive operating cycles are overlapping.
Claim 5
Dependent Claim
42 words
A system according to claim 1 including an interrupt latch in said microcomputer device, the control means switching said latch between enable and disable conditions in response to an instruction, and wherein said interrupt means is not controlled by the interrupt latch.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-04-29 | 1988-10-29 | 1989-04-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-04-29 | 1992-10-29 | 1993-04-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-04-29 | 1996-10-29 | 1997-04-30 | $7700.00 | Window Closed / Lapsed |