Method and apparatus for generating a repetitive serial pattern using a recirculating shift register

Claim 1

The method of generating a repetitive serial pattern using a recirculating shift register to reduce the amount of memory that would otherwise be required to hold a complete data pattern, said method comprising the steps of: a. initializing the memory to contain a subset of the complete data pattern to be serialized; b. reading a unit of data from the memory; c. loading the unit of data into a parallel to serial shift register; d. performing a parallel to serial conversion of the unit of data by shifting the unit of data in the shift register one bit at a time under the control of a bit clocking signal until all bits in the unit of data have been shifted out of a serial output of the parallel to serial shift register; e. returning to step b and reading the next unit of data from the memory under the control of a unit clocking signal until the last unit of data is read from the memory; f. detecting when the last unit of data is read from the memory and inhibiting the further loading of a unit of data from the memory into the parallel to serial shift register; and g. recirculating the last unit of data in the parallel to serial shift register by connecting the serial output to a serial input of the shift register, and continuing to recirculate the last unit of data and shifting out bits under control of the bit clocking signal until no more bits of data are required as determined by a count of the number of units of data output by the parallel to serial shift register.

Claim 2

The method of generating a repetitive serial pattern using a recirculating shift register to reduce the amount of memory that would otherwise be required to hold a complete data pattern, said method comprising the steps of: a. initializing the memory to contain a subset of the complete data pattern to be serialized; b. reading a unit of data from the memory; c. loading the unit of data into a parallel to serial shift register; d. performing a parallel to serial conversion of the unit of data by shifting the unit of data in the shift register one bit at a time under the control of a bit clocking signal until all bits in the unit of data have been shifted out of a serial output of the parallel to serial shift register; e. returning to step b and reading the next unit of data from the memory under the control of a unit clocking signal until the last unit of data is read from the memory; f. detecting when the last unit of data is read from the memory and inhibiting the further loading of a unit of data from the memory into the parallel to serial shift register; and g. recirculating the last unit of data in the parallel to serial shift register by connecting the serial output to a serial input of the shift register, and continuing to recirculate the last unit of data and shifting out bits under control of the bit clocking signal until no more bits of data are required as determined by a count of the number of units of data output by the parallel to serial shift register.

Claim 9

An apparatus for generating a repetitive serial pattern using a recirculating shift register comprising: a. a parallel to serial shift register having a serial output coupled to a serial input of said shift register; b. a memory capable of containing a plurality of units of data, an input/output port of said memory coupled to a parallel input/output port of said shift register; c. an initialization means for initializing the contents of said memory to contain said plurality of units of data; d. an incrementing address means having an address output coupled to an address input of said memory; e. a data unit clock generating means coupled to a count input of said incrementing address means; f. a bit clock generating means coupled to a clocking input of said parallel to serial shift register; and g. a load signal generating means coupled to a load input of said parallel to serial shift register whereby consecutive units of data are read from said memory and loaded into said parallel to serial shift register one unit of data at a time and serially shifted out of said serial output of said parallel to serial shift register to produce a serial bit stream until one complete unit of data has been shifted out one bit at a time in response to said bit clock generating means at which time said data unit clocking means causes said incrementing address register means to increment and causes said load signal generating means to load a next unit of data from said memory into said parallel to serial shift register and then said next unit of data is shifted out to continue production of said serial bit stream.

Claim 10

An apparatus for generating a repetitive serial pattern using a recirculating shift register comprising: a. a parallel to serial shift register having a serial output coupled to a serial input of said shift register; b. a memory capable of containing a plurality of units of data, an input/output port of said memory coupled to a parallel input/output port of said shift register; c. an initialization means for initializing the contents of said memory to contain said plurality of units of data; d. an incrementing address means having an address output coupled to an address input of said memory; e. a data unit clock generating means coupled to a count input of said incrementing address means; f. a bit clock generating means coupled to a clocking input of said parallel to serial shift register; and g. a load signal generating means coupled to a load input of said parallel to serial shift register whereby consecutive units of data are read from said memory and loaded into said parallel to serial shift register one unit of data at a time and serially shifted out of said serial output of said parallel to serial shift register to produce a serial bit stream until one complete unit of data has been shifted out one bit at a time in response to said bit clock generating means at which time said data unit clocking means causes said incrementing address register means to increment and causes said load signal generating means to load a next unit of data from said memory into said parallel to serial shift register and then said next unit of data is shifted out to continue production of said serial bit stream.