Method and an apparatus for generating periodic digital time function signals

Claim 1

In a method of obtaining digital periodic time function signals with the aid of a memory (3) having a plurality of storage cells, each time function signal having a first period (T), predetermined binary numbers stored in corresponding storage cells defining each periodic time function signal, the steps comprising for each of said digital periodic time function signals calculating a first group of binary numbers (x j ) representing relative time values of their positive and negative going edges by choosing for each of said relative time values an own zero reference point by taking into account the delay time of said memory (3), by using a second period (T 2 ) as a time unit, allotting to said binary numbers (x j ) a predetermined, normally not used binary number (255="11111111"), in each case an edge is not to be produced, assigning a prearranged number of said storage cells to each of said digital periodic time function signals to be obtained, storing each one of said first groups of binary numbers (x j ) in those of said storage cells which belong to said digital periodic time function signal, and in such an order of succession that increasing absolute time values related to said binary numbers (x j ) correspond to increasing values of memory addresses, whereby said absolute time values correspond to said relative time values with the difference that the absolute time values have a single zero reference point common for all of them, generating a first clock signal (CL1) for resetting purposes, having a period (T 1 ) equal to said first period (T) of said digital periodic time function signals, generating a second clock signal (CL2) having said second period (T 2 ), which has a predetermined relationship to said first period (T), deriving from said second clock signal (CL2) a third clock signal (CL3), having a third period (T 3 ) which is a multiple of said second period (T 2 ), binary counting the number of said third periods (T 3 ) with the aid of an address counter (2) and allotting this second group of binary numbers to said memory addresses of said storage cells, successive calling up said different storage cells belonging to said digital periodic time function signal, with the aid of said second group of binary numbers and the address inputs of said memory (3), and thereby successively reading of said binary numbers (x j ) of said first group of binary numbers out of said memory (3), successive parallel loading said binary numbers (x j ) of said first group of binary numbers in period counters (4; 5), delayed enabling between each of said loadings during an enabling time interval, only the counting of one of said period counters (4; 5) with the aid of a logic circuit (12), if an edge of said digital periodic time function signal which belongs to said one period counter must be produced during said enabling time interval, counting the number of second periods (T 2 ) during said enabling time beginning with said loaded binary number (x j ) of said first group of binary numbers until a predetermined reference number is reached, in the moment of reaching said predetermined reference number, inverting the digital instantaneous value of said digital periodic time function signal at the output of a D-flip-flop (6; 7) with the aid of this D-flip-flop.