CMOS/SOS transistor gate array apparatus

Claim 2

An integrated circuit transistor gate array comprising, in combination: a substrate; an array of groups of transistor gates, each transistor gate comprising a source, a drain and a control lead, fabricated on the substrate wherein each group comprises three contiguous transistor gates of a first polarity type connected in a drain-source series arrangement, two isolated transistor gates of said first polarity type, three contiguous transistor gates of a second polarity type connected in a drain-source series arrangement, and two isolated transistor gates of said second polarity type; first means, attached to said substrate, connecting the control lead of each transistor gate of said first polarity to a control lead of a corresponding transistor gate of the second polarity in the group; and insulation means covering a portion of said first means between said control leads whereby further leads can be attached to said substrate to interconnect noncontiguous transistor gates separated by said first means.

Claim 3

An integrated circuit FET transistor array comprising, in combination: a substrate having a plane surface with X and Y dimensions; first groups of FET transistors, each transistor in a group including source, drain and gate means, fabricated on the substrate wherein each group comprises three contiguous transistors of a first polarity connected in a drain-source series arrangement and three contiguous transistors of a second polarity connected in a drain-source series arrangement; and second groups of FET transistors, each transistor in a group including source, drain and gate means, fabricated on the substrate between said first groups of FET transistors, said second group comprising two isolated transistors of a first polarity and two isolated transistors of a second polarity, said array comprising alternating first and second groups of transistors in both the X and Y directions on the surface of said substrate.

Claim 4

An integrated circuit FET transistor array comprising, in combination: a substrate having a plane surface with X and Y dimensions; first groups of FET transistors, each transistor in a group including source, drain and gate means, fabricated on the substrate wherein each group comprises three contiguous transistors of a first polarity connected in a drain-source series arrangement and three contiguous transistors of a second polarity connected in a drain-source series arrangement; and second groups of FET transistors, each transistor in a group including source, drain and gate means, fabricated on the substrate between said first groups of FET transistors, said second group comprising two isolated transistors of a first polarity and two isolated transistors of a second polarity, said array comprising alternating first and second groups of transistors in both the X and Y directions on the surface of said substrate.

Claim 5

A transistor array comprising, in combination: substrate means; first and second columns of CMOS/SOS transistors on said substrate means, each transistor in each of said columns including gate lead means and gate contact means extending on said substrate means in an outwardly direction from said column means wherein at least a portion of said gate lead means is insulated; interconnect means situated on said substrate means for providing electrical connections between transistors in different columns, said interconnect means comprising interconnect contact means and interconnect insulated portions, the insulated portions of said gate lead means and said interconnect means being adapted to having further leads attached to said substrate means and passing over said insulated portions, said gate contact means and said interconnect contact being interleaved to form further columns juxtaposed said columns of transistors; and said transistors in said columns are grouped to have a repeating arrangement of three pairs of series connected complementary transistors and two pairs of independent complementary transistors both in said columns of transistors and across said columns of transistors.

Claim 6

A transistor array comprising, in combination: substrate means; first and second columns of CMOS/SOS transistors on said substrate means, each transistor in each of said columns including gate lead means and gate contact means extending on said substrate means in an outwardly direction from said column means wherein at least a portion of said gate lead means is insulated; interconnect means situated on said substrate means for providing electrical connections between transistors in different columns, said interconnect means comprising interconnect contact means and interconnect insulated portions, the insulated portions of said gate lead means and said interconnect means being adapted to having further leads attached to said substrate means and passing over said insulated portions, said gate contact means and said interconnect contact being interleaved to form further columns juxtaposed said columns of transistors; and said transistors in said columns are grouped to have a repeating arrangement of three pairs of series connected complementary transistors and two pairs of independent complementary transistors both in said columns of transistors and across said columns of transistors.

Claim 7

A universal array of transistors manufactured with provisions for later definition of specific circuits incorporating transistors in said array comprising, in combination: a plurality of first cells of transistors each of said first cells including, three series connected P channel type transistors, three series connected N channel type transistors, and common gate leads interconnecting similarly situated ones of said P channel type and N channel type transistors, said common gate leads having contact areas between connected transistors, said contact areas alternating in proximity to given channel type transistors; and a plurality of second cells of transistors each of said second cells including, two independent P channel type transistors, two independent N channel type transistors, and common gate leads interconnecting similarly situated ones of said P channel type and N channel type transistors, said common gate leads having contact areas between connected transistors, said contact areas alternating in proximity to given channel type transistors.

Claim 8

A universal array of transistors manufactured with provisions for later definition of specific circuits incorporating transistors in said array comprising, in combination: a plurality of first cells of transistors each of said first cells including, three series connected P channel type transistors, three series connected N channel type transistors, and common gate leads interconnecting similarly situated ones of said P channel type and N channel type transistors, said common gate leads having contact areas between connected transistors, said contact areas alternating in proximity to given channel type transistors; and a plurality of second cells of transistors each of said second cells including, two independent P channel type transistors, two independent N channel type transistors, and common gate leads interconnecting similarly situated ones of said P channel type and N channel type transistors, said common gate leads having contact areas between connected transistors, said contact areas alternating in proximity to given channel type transistors.

Claim 9

A universal array of transistors manufactured with provisions for later definition of specific circuits incorporating transistors in said array comprising, in combination: a plurality of first cells of transistors each of said first cells including, three series connected P channel type transistors, three series connected N channel type transistors, and common gate leads interconnecting similarly situated ones of said P channel type and N channel type transistors, said common gate leads having contact areas between connected transistors, said contact areas alternating in proximity to given channel type transistors; a plurality of second cells of transistors each of said second cells including, two independent P channel type transistors, two independent N channel type transistors, and common gate leads interconnecting similarly situated ones of said P channel type and N channel type transistors, said common gate leads having contact areas between connected transistors, said contact areas alternating in proximity to given channel type transistors; first interconnect leads, including first, second and third contact areas, situated near the end of given cells within columns between sets of second interconnect leads in the same column as said first interconnect leads having first and second contact areas which are aligned columnarly with said first and second contact areas of said first interconnect leads; and third interconnect leads situated in the same columns as said first and second interconnect leads, said third interconnect leads including two contact areas aligned columnarly with said second and third contact areas of said first interconnect leads, said second and third interconnect leads being substantially one-half the length of said first interconnect leads and said second interconnect leads being closer to one side of said column and said third interconnect leads being closer to the other side of said column.

Claim 10

A universal array of transistors manufactured with provisions for later definition of specific circuits incorporating transistors in said array comprising, in combination: a plurality of first cells of transistors each of said first cells including, three series connected P channel type transistors, three series connected N channel type transistors, and common gate leads interconnecting similarly situated ones of said P channel type and N channel type transistors, said common gate leads having contact areas between connected transistors, said contact areas alternating in proximity to given channel type transistors; a plurality of second cells of transistors each of said second cells including, two independent P channel type transistors, two independent N channel type transistors, and common gate leads interconnecting similarly situated ones of said P channel type and N channel type transistors, said common gate leads having contact areas between connected transistors, said contact areas alternating in proximity to given channel type transistors; first interconnect leads, including first, second and third contact areas, situated near the end of given cells within columns between sets of second interconnect leads in the same column as said first interconnect leads having first and second contact areas which are aligned columnarly with said first and second contact areas of said first interconnect leads; and third interconnect leads situated in the same columns as said first and second interconnect leads, said third interconnect leads including two contact areas aligned columnarly with said second and third contact areas of said first interconnect leads, said second and third interconnect leads being substantially one-half the length of said first interconnect leads and said second interconnect leads being closer to one side of said column and said third interconnect leads being closer to the other side of said column.

Claim 11

Apparatus as claimed in claim 5 comprising, in addition end contacts on said common gate leads of said plurality of cells of transistors being columnarly aligned with said contact areas of said interconnect means on opposite sides of columns defining said plurality of first cells of transistors.

Claim 12

Apparatus as claimed in claim 6 wherein said end contacts are positioned a distance away from the transistors in said cells sufficient to permit later defining of conductive paths between said end contacts and the body of the transistor.

Claim 13

An integrated circuit transistor gate array comprising, in combination: a substrate; an array of groups of transistor gates, each transistor gate comprising a source, a drain and a control lead, fabricated on the substrate wherein each group comprises three contiguous transistor gates of a first polarity type connected in a drain-source series arrangement, two isolated transistor gates of said first polarity type, three contiguous transistor gates of a second polarity type connected in a drain-source series arrangement, and two isolated transistor gates of said second polarity type; first means, attached to said substrate, connecting the control lead of each transistor gate of said first polarity type to a control lead of a corresponding transistor gate of the second polarity type in the group; and insulation means covering a portion of said first means between said control leads whereby further leads can be attached to said substrate to interconnect noncontiguous transistor gates separated by said first means.

Claim 14

An integrated circuit transistor gate array comprising, in combination: a substrate; an array of groups of transistor gates, each transistor gate comprising a source, a drain and a control lead, fabricated on the substrate wherein each group comprises three contiguous transistor gates of a first polarity type connected in a drain-source series arrangement, two isolated transistor gates of said first polarity type, three contiguous transistor gates of a second polarity type connected in a drain-source series arrangement, and two isolated transistor gates of said second polarity type; first means, attached to said substrate, connecting the control lead of each transistor gate of said first polarity type to a control lead of a corresponding transistor gate of the second polarity type in the group; and insulation means covering a portion of said first means between said control leads whereby further leads can be attached to said substrate to interconnect noncontiguous transistor gates separated by said first means.

Claim 15

An integrated circuit FET transistor array comprising, in combination: a substrate having a plane surface with X and Y dimensions; first groups of FET transistors, each transistor in a group including source, drain and gate means, fabricated on the substrate wherein each group comprises three contiguous transistors of a first polarity type connected in a drain-source series arrangement and three contiguous transistors of a second polarity type connected in a drain-source series arrangement; and second groups of FET transistors, each transistor in a group including source, drain and gate means, fabricated on the substrate between said first groups of FET transistors, said second group comprising two isolated transistors of a first polarity type and two isolated transistors of a second polarity type, said array comprising alternating first and second groups of transistors in both the X and Y directions on the surface of said substrate.

Claim 16

An integrated circuit FET transistor array comprising, in combination: a substrate having a plane surface with X and Y dimensions; first groups of FET transistors, each transistor in a group including source, drain and gate means, fabricated on the substrate wherein each group comprises three contiguous transistors of a first polarity type connected in a drain-source series arrangement and three contiguous transistors of a second polarity type connected in a drain-source series arrangement; and second groups of FET transistors, each transistor in a group including source, drain and gate means, fabricated on the substrate between said first groups of FET transistors, said second group comprising two isolated transistors of a first polarity type and two isolated transistors of a second polarity type, said array comprising alternating first and second groups of transistors in both the X and Y directions on the surface of said substrate.

Claim 17

A transistor array comprising, in combination: substrate means; first and second columns of transistors on said substrate means, each transistor in each of said columns including gate lead means and gate contact means extending on said substrate means in an outwardly direction from said column means wherein at least a portion of said gate lead means is insulated; interconnect means situated on said substrate means for providing electrical connections between transistors in different columns, said interconnect means comprising interconnect contact means and interconnect insulated portions, the insulated portions of said gate lead means and said interconnect means being adapted to having further leads attached to said substrate means and passing over said insulated portions, said gate contact means and said interconnect contact being interleaved to form further columns juxtaposed said columns of transistors; and said transistors in said columns are CMOS/SOS and are grouped to have a repeating arrangement of three pairs of series connected complementary transistors and two pairs of independent complementary transistors both in said columns of transistors and in rows across said columns of transistors.

Claim 18

A transistor array comprising, in combination: substrate means; first and second columns of transistors on said substrate means, each transistor in each of said columns including gate lead means and gate contact means extending on said substrate means in an outwardly direction from said column means wherein at least a portion of said gate lead means is insulated; interconnect means situated on said substrate means for providing electrical connections between transistors in different columns, said interconnect means comprising interconnect contact means and interconnect insulated portions, the insulated portions of said gate lead means and said interconnect means being adapted to having further leads attached to said substrate means and passing over said insulated portions, said gate contact means and said interconnect contact being interleaved to form further columns juxtaposed said columns of transistors; and said transistors in said columns are CMOS/SOS and are grouped to have a repeating arrangement of three pairs of series connected complementary transistors and two pairs of independent complementary transistors both in said columns of transistors and in rows across said columns of transistors.