Method for manufacturing a monolithically integrable circuit with a multilayer wiring structure

Abstract

Abstract A method of manufacturing a monolithically integrable circuit, which includes depositing an SiO 2 layer on the surface of a semiconductor substrate containing p-n junctions of the circuit, at least partially covering the SiO 2 layer with a first metallization supported by the SiO 2 layer and containing conductor runs and electrodes capacitively coupled to the surface of the semiconductor substrate through the SiO 2 layer, directly covering the first metallization with a sputtered-on SiO 2 insulating layer after the first metallization is completed, covering the sputtered-on SiO 2 layer with a further inorganic insulating layer generated by the plasma method, structuring the further inorganic insulating layer and the sputtered-on SiO 2 layer, forming cutouts in the further inorganic insulating layer and the sputtered-on SiO 2 layer above intended contact locations of the first metallization, applying a second metallization to the surface of the further inorganic insulating layer after completing the first metallization, the sputtered-on SiO 2 layer and the further inorganic insulating layer, bringing the second metallization into electrical contact with the contact locations of the first metallization through the cutouts, and forming the second metallization into conductor runs.

Inventors

• 👤 Harald Eggers

Bibliographic Details