MOS Analog switch driven by complementary, minimally skewed clock signals

Claim 2

An MOS analog switch, comprising: first, second and third MOS transmission gates, each transmission gate having a transistor of first conductivity type utilizing a first current electrode as an input terminal, a second current electrode as an output terminal, and a control electrode, the input terminals of the first, second and third transmission gates connected together to form an input of said switch, the output terminals of the second and third transmission gates connected together to form an output of said switch, and the output terminal of said first transmission gate connected to both input terminals of said second and third transmission gates; and clock means for providing a clock signal to the control electrodes of said second and third transmission gates, and for providing a complement clock signal to the control electrode of said first transmission gate, comprising: first inverter means having an input for receiving a control signal, and an output for providing said complement clock signal; and second inverter means having an input coupled to the output of said first inverter means and an output for providing said clock signal, wherein: said first and second inverter means have transistors with control electrode dimensions ratioed in a predetermined manner to minimize the delay between said clock signal and its complement.

Claim 3

The CMOS analog switch of claim 1 wherein said first inverter means comprise a first MOS transistor of either said first conductivity type or a second conductivity type having a control electrode of predetermined dimensions and a second MOS transistor of opposite conductivity type from said first MOS transistor having a control electrode with dimensions at least three times smaller than the dimensions of the control electrode of said first MOS transistor, and said second inverter means comprise a third MOS transistor of same conductivity type as said first MOS transistor having a control electrode of predetermined dimensions and a fourth MOS transistor of same conductivity type as said second MOS transistor having a control electrode with dimensions at least three times larger than the dimensions of the control electrode of said third MOS transistor.

Claim 4

The CMOS analog switch of claim 2 wherein the dimensions of the control electrode of the second MOS transistor of said second conductivity type of said first inverter means are substantially ten times smaller than the dimensions of the control electrode of the first MOS transistor of said first conductivity type of said first inverter means.

Claim 5

The CMOS analog switch of claim 2 wherein the dimensions of the control electrode of the fourth MOS transistor of said second conductivity type of said second inverter means are substantially ten times greater than the dimensions of the control electrode of the third MOS transistor of said first conductivity type of said second inverter means.

Claim 6

A CMOS analog switch, comprising: first, second and third CMOS transmission gates, each CMOS transmission gate having two transistors of opposite conductivity type coupled in parallel to form an input terminal, an output terminal and first and second control electrodes, the input terminals of the first, second and third transmission gates connected together to form an input of said switch, the output terminals of the second and third transmission gates connected together to form an output of said switch, and the output terminal of said first transmission gate connected to both input terminals of said second and third transmission gates; and clock means for providing a clock signal to the first control electrode of said first transmission gate and to the second control electrodes of said second and third transmission gates, and for providing a complement clock signal to the second control electrode of said first transmission gate and to the first control electrode of said second and third transmission gates, comprising: first inverter means having an input for receiving said clock signal, and an output for providing said complement clock signal; and second inverter means having an input coupled to the output of said first inverter means and an output, wherein: said first and second inverter means have transistors with control electrode dimensions ratioed in a predetermined manner to minimize the delay between said clock signal and its complement.

Claim 7

A CMOS analog switch, comprising: first, second and third CMOS transmission gates, each CMOS transmission gate having two transistors of opposite conductivity type coupled in parallel to form an input terminal, an output terminal and first and second control electrodes, the input terminals of the first, second and third transmission gates connected together to form an input of said switch, the output terminals of the second and third transmission gates connected together to form an output of said switch, and the output terminal of said first transmission gate connected to both input terminals of said second and third transmission gates; and clock means for providing a clock signal to the first control electrode of said first transmission gate and to the second control electrodes of said second and third transmission gates, and for providing a complement clock signal to the second control electrode of said first transmission gate and to the first control electrode of said second and third transmission gates, comprising: first inverter means having an input for receiving said clock signal, and an output for providing said complement clock signal; and second inverter means having an input coupled to the output of said first inverter means and an output, wherein: said first and second inverter means have transistors with control electrode dimensions ratioed in a predetermined manner to minimize the delay between said clock signal and its complement.

Claim 8

The CMOS analog switch of claim 5 wherein said first inverter means comprise a first MOS transistor of a first conductivity type having a control electrode of predetermined dimensions and a second MOS transistor of a second conductivity type having a control electrode with dimensions at least three times smaller than the dimensions of the control electrode of said first MOS transistor, and said second inverter means comprise a third MOS transistor of said first conductivity type having a control electrode of predetermined dimensions and a fourth MOS transistor of said second conductivity type having a control electrode with dimensions at least three times larger than the dimensions of the control electrode of said third MOS transistor.

Claim 9

The CMOS analog switch of claim 6 wherein the dimensions of the control electrode of the second MOS transistor of said second conductivity type of said first inverter means are substantially ten times smaller than the dimensions of the control electrode of the first MOS transistor of said first conductivity type of said first inverter means.

Claim 10

The CMOS analog switch of claim 6 wherein the dimensions of the control electrode of the fourth MOS transistor of said second conductivity type of said second inverter means are substantially ten times greater than the dimensions of the control electrode of the third MOS transistor of said first conductivity type of said second inverter means.

Claim 13

A composite solid state switch, comprising: a first transmission gate having a first N-channel transistor with a first current electrode coupled to a first current electrode of a first P-channel transistor, a second current electrode coupled to a second current electrode of said first P-channel transistor, and a control electrode for receiving a control signal, said first P-channel transistor having a control electrode for receiving the complement of said control signal; a second transmission gate having a second N-channel transistor with a first current electrode coupled to a first current electrode of a second P-channel transistor and to the first current electrodes of said first N-channel and P-channel transistors to form an input terminal of said switch, a second current electrode coupled to a second current electrode of said second P-channel transistor and to the second current electrodes of said first N-channel and P-channel transistors to form an output terminal of said switch, and a control electrode for receiving said control signal, said second P-channel transistor having a control electrode for receiving the complement of said control signal; a third transmission gate, for compensating for error voltages associated with said first and second transmission gates, having a third N-channel transistor with a first current electrode coupled to a first current electrode of a third P-channel transistor and to said input terminal, a second current electrode coupled to a second current electrode of said third P-channel transistor and to said input terminal, and a control electrode for receiving the complement of said control signal, said third P-channel transistor having a control electrode for receiving said control signal; a first inverter having an input for receiving a clock signal and an output for providing the complement of said control signal, comprising a fourth P-channel transistor coupled to a fourth N-channel transistor, said fourth P-channel and N-channel transistors having control electrodes of predetermined dimensions wherein the control electrode dimensions of said fourth P-channel transistor is at least three times greater than the dimensions of the control electrode of said fourth N-channel transistor; and a second inverter having an input for receiving the complement of said control signal and an output for providing said control signal, comprising a fifth P-channel transistor coupled to a fifth N-channel transistor, said fifth P-channel and N-channel transistors having control electrodes of predetermined dimensions wherein the control electrode dimensions of said fifth N-channel transistor is at least three times greater than the control electrode dimensions of said fifth P-channel transistor.

Claim 14

A composite solid state switch, comprising: a first transmission gate having a first N-channel transistor with a first current electrode coupled to a first current electrode of a first P-channel transistor, a second current electrode coupled to a second current electrode of said first P-channel transistor, and a control electrode for receiving a control signal, said first P-channel transistor having a control electrode for receiving the complement of said control signal; a second transmission gate having a second N-channel transistor with a first current electrode coupled to a first current electrode of a second P-channel transistor and to the first current electrodes of said first N-channel and P-channel transistors to form an input terminal of said switch, a second current electrode coupled to a second current electrode of said second P-channel transistor and to the second current electrodes of said first N-channel and P-channel transistors to form an output terminal of said switch, and a control electrode for receiving said control signal, said second P-channel transistor having a control electrode for receiving the complement of said control signal; a third transmission gate, for compensating for error voltages associated with said first and second transmission gates, having a third N-channel transistor with a first current electrode coupled to a first current electrode of a third P-channel transistor and to said input terminal, a second current electrode coupled to a second current electrode of said third P-channel transistor and to said input terminal, and a control electrode for receiving the complement of said control signal, said third P-channel transistor having a control electrode for receiving said control signal; a first inverter having an input for receiving a clock signal and an output for providing the complement of said control signal, comprising a fourth P-channel transistor coupled to a fourth N-channel transistor, said fourth P-channel and N-channel transistors having control electrodes of predetermined dimensions wherein the control electrode dimensions of said fourth P-channel transistor is at least three times greater than the dimensions of the control electrode of said fourth N-channel transistor; and a second inverter having an input for receiving the complement of said control signal and an output for providing said control signal, comprising a fifth P-channel transistor coupled to a fifth N-channel transistor, said fifth P-channel and N-channel transistors having control electrodes of predetermined dimensions wherein the control electrode dimensions of said fifth N-channel transistor is at least three times greater than the control electrode dimensions of said fifth P-channel transistor.

Claim 15

The composite solid state switch of claim 10 wherein the control electrode dimensions of the fourth P-channel transistor are substantially ten times larger than the control electrode dimensions of said fourth N-channel transistor.

Claim 16

The composite solid state switch of claim 10 wherein the control electrode dimensions of the fifth N-channel transistor are substantially ten times larger than the control electrode dimensions of said fifth P-channel transistor.