US4507749A
Expired / Lapsed
US
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Two's complement multiplier circuit
Assignee: Toshiba Corp
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Filing: 1982-09-24
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Granted: 1985-03-26
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Expires: 2002-09-24
Abstract
Abstract A multiplication circuit includes a multiplying unit for multiplying a signed multiplier X represented in terms of the two's complement of n bits by a signed multiplicand Y represented in terms of two's complement of n bits to generate a signed multiplication output data of (2n-1) bits represented in terms of the two's complement, an exclusive-OR circuit for producing the exclusive-OR of the sign bits XS and YS of the respective values X and Y, and a selecting circuit for generating a sign bit "0" when the most significant bit of the multiplication output data from the multiplying unit is "0" and generating as a sign bit an output bit of the exclusive-OR circuit when the most significant bit is "1".
Inventors
- 👤 Masahide Ohhashi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 22:21
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/52; G06F7/523
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
171 words
A digital multiplication circuit comprising: multiplication means for multiplying a multiplier X of a signed binary code represented in terms of the two's complement of n bits by a multiplicand Y of a signed binary code represented in terms of the two's complement of n bits to thereby generate a multiplication output data of binary code represented in terms of the two's complement; sign bit generating means for generating an output bit "0" when a sign bit X S of the multiplier, a sign bit Y S of the multiplicand Y and a bit M1 in a (2n-1)th bit position from the least significant bit position of the multiplication output data from said multiplication means are all "1" and generating an output bit equal to the (2n-1)th bit M1 when at least one of the bits X S , Y S and M1 is "0", whereby the multiplication output data from said multiplication means is a numeral and the output bit from said sign bit generating means is a sign bit.
Claim 2
Dependent Claim
171 words
A digital multiplication circuit comprising: multiplication means for multiplying a multiplier X of a signed binary code represented in terms of the two's complement of n bits by a multiplicand Y of a signed binary code represented in terms of the two's complement of n bits to thereby generate a multiplication output data of binary code represented in terms of the two's complement; sign bit generating means for generating an output bit "0" when a sign bit X S of the multiplier, a sign bit Y S of the multiplicand Y and a bit M1 in a (2n-1)th bit position from the least significant bit position of the multiplication output data from said multiplication means are all "1" and generating an output bit equal to the (2n-1)th bit M1 when at least one of the bits X S , Y S and M1 is "0", whereby the multiplication output data from said multiplication means is a numeral and the output bit from said sign bit generating means is a sign bit.
Claim 3
Dependent Claim
48 words
A multiplication circuit according to claim 1, wherein said multiplication means is an n×n bit multiplier of an array type for generating a multiplication output data of (2n-1) bits having a sign bit M1 in the (2n-1)th bit position and a numeral section of the following (2n-2) bits.
Claim 4
Dependent Claim
88 words
A multiplication circuit according to claim 1 or 2, wherein said sign bit generating means comprises: an exclusive-OR cicuit for generating an output bit equal to the exclusive-OR of the sign X S of the multiplier X and the sign bit Y S of the multiplicand Y; and selecting means for generating an output bit "0" when the (2n-1)th bit M1 of the multiplication output data from said multiplication means is "0" and selecting an output bit of the exclusive-OR circuit when the (2n-1)th bit M1 is "1".
Claim 5
Dependent Claim
86 words
A multiplication circuit according to claim 3, wherein said selecting means comprises: an output node; a p-channel MOS transistor having a current path coupled between the output node and a ground point and a gate for receiving the (2n-1)th bit M1 of the multiplication output data from said multiplication means; and an n-channel MOS transistor having a current path coupled between the output node and the output terminal of said exclusive-OR circuit and a gate for receiving the (2n-1)th bit M1 of the multiplication output data.
Claim 6
Dependent Claim
57 words
A multiplication circuit according to claim 1 or 2, wherein said sign bit generating means comprises: a NAND circuit for receiving the sign bits X S and Y S ; and an AND circuit for receiving an output bit from said NAND circuit and the (2n-1)th bit M1 of the multiplication output data from said multiplication means.
References Cited (Backward Citations)
US3866030A
Cited
US4086474A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-03-25 | 1988-09-24 | 1989-03-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-03-25 | 1992-09-24 | 1993-03-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-03-25 | 1996-09-24 | 1997-03-26 | $7700.00 | Window Closed / Lapsed |