US3866030A
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Two{3 s complement parallel array multiplier
Assignee: AT&T Inc
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Filing: 1974-04-01
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Granted: 1975-02-11
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Expires: 1994-04-01
Abstract
Abstract Apparatus and methods for performing the parallel m-bit by n-bit multiplication of two binary 2''s complement numbers by converting the multiplication process to an equivalent parallel array addition in which the operands are positive partial products including (1) terms formed by ANDing a multiplier bit (or its complement), and (2) a multiplicand bit (or its complement) and five additional partial product terms. The resulting simplifications permit circuit realization in the form of an array of 3-bit adders each formed from a combination of threshold logic modules.
Inventors
- 👤 Charles Richmond Baugh
- 👤 Bruce Allen Wooley
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 15:49
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/52; G06F7/523; G06F7/53; G06F7/5318; G06F7/50; G06F7/505; G06F7/506; G06F2207/00; G06F2207/38; G06F2207/48; G06F2207/4802; G06F2207/4818
Claims Analysis
Total Claims: 35
Claim 1
Independent Claim
104 words
Apparatus for forming the product, P (pn m 1, Pm n 2, . . . ,p0), of an m-bit 2''s complement multiplicand, Y (ym 1, ym 2, . . . ,y0), and an n-bit 2''s complement multiplier, X (xn 1, xn 2, . . . ,x0), comprising A. first means for forming partial product terms xiyj for all i and j yielding positive values, B. second means for forming partial product terms having positive values equivalent to those xiyj which are negative, and C. third means for combining said partial product terms formed by said first and second means to form said product P.
Claim 2
Dependent Claim
104 words
Apparatus for forming the product, P (pn m 1, Pm n 2, . . . ,p0), of an m-bit 2''s complement multiplicand, Y (ym 1, ym 2, . . . ,y0), and an n-bit 2''s complement multiplier, X (xn 1, xn 2, . . . ,x0), comprising A. first means for forming partial product terms xiyj for all i and j yielding positive values, B. second means for forming partial product terms having positive values equivalent to those xiyj which are negative, and C. third means for combining said partial product terms formed by said first and second means to form said product P.
Claim 3
Dependent Claim
33 words
Apparatus according to claim 1 wherein said first means comprises a plurality of 2-input AND gates, and means for applying one bit xi and one bit yj to each of said AND gates.
Claim 4
Dependent Claim
13 words
means for complementing each multiplier bit xi to form a corresponding bit x1,
Claim 5
Dependent Claim
13 words
means for complementing each multiplier bit xi to form a corresponding bit x1,
Claim 6
Dependent Claim
21 words
forming pm n 1 by adding 1 to the carry resulting from the summing for k n + m - 2.
Claim 7
Dependent Claim
21 words
forming pm n 1 by adding 1 to the carry resulting from the summing for k n + m - 2.
Claim 8
Dependent Claim
18 words
forming the AND of ym 1 and xi for i 0,1, . . . ,n - 2, and
Claim 9
Dependent Claim
18 words
forming the AND of ym 1 and xi for i 0,1, . . . ,n - 2, and
Claim 10
Dependent Claim
14 words
forming as partial products xn 1, xn 1, ym 1, ym 1, and 1.
Claim 11
Dependent Claim
14 words
forming as partial products xn 1, xn 1, ym 1, ym 1, and 1.
Claim 12
Dependent Claim
6 words
a plurality of 2-input AND gates,
Claim 13
Dependent Claim
6 words
a plurality of 2-input AND gates,
Claim 14
Dependent Claim
10 words
Apparatus according to claim 1 wherein said second means comprises
Claim 15
Dependent Claim
22 words
means for applying xn 1 to one input of each of a first set of m - 1 of said AND gates,
Claim 16
Dependent Claim
22 words
means for applying xn 1 to one input of each of a first set of m - 1 of said AND gates,
Claim 17
Dependent Claim
22 words
Apparatus according to claim 3 wherein said second means further comprises means for generating a partial product having the constant value 1.
Claim 18
Dependent Claim
23 words
Apparatus according to claim 1 wherein said third means comprises means for selectively adding said terms formed by said first and second means.
Claim 19
Dependent Claim
35 words
means for applying one of the bits yj, j 0,1, . . . ,m - 2 to the other input of respective ones of said m-1 AND gates in said first set of AND gates,
Claim 20
Dependent Claim
35 words
means for applying one of the bits yj, j 0,1, . . . ,m - 2 to the other input of respective ones of said m-1 AND gates in said first set of AND gates,
Claim 21
Dependent Claim
23 words
means for applying ym 1 to one input of each of a second set of n - 1 of said AND gates, and
Claim 22
Dependent Claim
23 words
means for applying ym 1 to one input of each of a second set of n - 1 of said AND gates, and
Claim 23
Dependent Claim
18 words
Apparatus according to claim 5 wherein said means for adding comprises an interconnected array of substantially identical adders.
Claim 24
Dependent Claim
16 words
Apparatus according to claim 6 wherein each of said substantially identical adders comprises a 3-bit adder.
Claim 25
Dependent Claim
33 words
means for applying xi, i 0,1, . . . ,n - 2 to the other input of respective ones of said n - 1 AND gates in said second set of AND gates.
Claim 26
Dependent Claim
33 words
means for applying xi, i 0,1, . . . ,n - 2 to the other input of respective ones of said n - 1 AND gates in said second set of AND gates.
Claim 27
Dependent Claim
18 words
Apparatus according to claim 6 wherein each of said adders comprises an interconnected plurality of threShold logic circuits.
Claim 28
Dependent Claim
14 words
Apparatus according to claim 8 wherein each of said adders comprises a 3-bit adder.
Claim 29
Dependent Claim
101 words
In a digital processing system, the machine method for forming the product, P (pn m 1, pn m 2, . . . ,p0), of an m-bit 2''s complement multiplicand, Y (ym 1, ym 2, . . . ,y0), and an n-bit 2''s complement multiplier, X (xn 1, Xn 2, . . . ,x0) comprising the steps of A. forming partial product terms xiyj for all i and j which yield positive values, B. forming positive partial product terms equivalent to those xiyj which are negative, and C. combining said partial product terms formed at steps (A) and (B) to produce P.
Claim 30
Dependent Claim
101 words
In a digital processing system, the machine method for forming the product, P (pn m 1, pn m 2, . . . ,p0), of an m-bit 2''s complement multiplicand, Y (ym 1, ym 2, . . . ,y0), and an n-bit 2''s complement multiplier, X (xn 1, Xn 2, . . . ,x0) comprising the steps of A. forming partial product terms xiyj for all i and j which yield positive values, B. forming positive partial product terms equivalent to those xiyj which are negative, and C. combining said partial product terms formed at steps (A) and (B) to produce P.
Claim 31
Dependent Claim
10 words
The method of claim 10 wherein said step (B) comprises
Claim 32
Dependent Claim
118 words
Apparatus for forming the product, P (pn m 1, pn m 2, . . . ,p0), of an m-bit 2''s complement multiplicand, Y (ym 1, ym 2, . . . ,y0), and an n-bit 2''s complement multiplier, X (xn 1, xn 2, . . . ,x0) comprising A. means for forming the positive partial products xiyj, for 0 < or = i < or = n - 2; xn 1yj, for 0 < or = j < or = m - 2; xiym 1, for 0 < or = i < or = n - 2; xn 1, xn 1, ym 1, ym 1, 1, and xn 1ym 1, and B. means for selectively combining said partial products.
Claim 33
Dependent Claim
118 words
Apparatus for forming the product, P (pn m 1, pn m 2, . . . ,p0), of an m-bit 2''s complement multiplicand, Y (ym 1, ym 2, . . . ,y0), and an n-bit 2''s complement multiplier, X (xn 1, xn 2, . . . ,x0) comprising A. means for forming the positive partial products xiyj, for 0 < or = i < or = n - 2; xn 1yj, for 0 < or = j < or = m - 2; xiym 1, for 0 < or = i < or = n - 2; xn 1, xn 1, ym 1, ym 1, 1, and xn 1ym 1, and B. means for selectively combining said partial products.
Claim 34
Dependent Claim
15 words
Apparatus according to claim 12 wherein said means for selectively combining comprises summing means for
Claim 35
Dependent Claim
16 words
Apparatus according to claim 13 wherein said summing means comprises an array of substantially identical adders.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-02-10 | 1978-08-12 | 1979-02-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-02-10 | 1982-08-12 | 1983-02-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-02-10 | 1986-08-12 | 1987-02-11 | $7700.00 | Window Closed / Lapsed |