Patent US4507576A successfully refreshed from Google Patents.
US4507576A
Expired / Lapsed
US
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Method and apparatus for synthesizing a drive signal for active IC testing including slew rate adjustment
Assignee: Credence Systems Corp
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Filing: 1982-10-28
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Granted: 1985-03-26
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Expires: 2002-10-28
Abstract
Abstract A special purpose pulse amplifier with programmable high and low levels for complex IC testing is disclosed. Its output has independently programmable positive and negative transition rates and is reverse terminated in 50 ohms. It also has the ability to be switched to a high resistance, low capacitance output state. This circuit is the interface between a complex, computer controlled system of timing and pattern generation hardware, and an integrated circuit to be tested. This device has reduced waveform aberrations, lower inhibited capacitance, low input to output delay for reducing timing error, programmable signal transition rates, and the amplitude range and transition rate control to accommodate all the important device technologies expected in high pin-count parts.
Inventors
- 👤 David R. McCracken
- 👤 Robin R. Larson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 10:48
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/319; G01R31/31917; G01R31/31924; G01R31/31903; G01R31/31908
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
197 words
A pulse converter circuit for converting a first digital signal compatible with a first logic family having first predetermined high and low logic levels and positive and negative slew rates, to a second digital signal compatible with a second logic family having second predetermined high and low logic levels and positive and negative slew rates, said circuit comprising: first means for receiving said first digital signal, and signals representative of the predetermined high and low logic levels and the positive and negative slew rates compatible with the second logic family; first voltage translator means for continuously detecting the logic state and state transitions of said first digital signal; slew rate adjustment means for establishing logic state transition rates in response to the predetermined positive and negative slew rate representative signals at the transition times detected by said voltage translator means; first clamp means for establishing the high and low logic levels of the second digital signal in response to the signals representative of the predetermined high and low logic levels, and the transition rates established by the slew rate adjustment means; and output means coupled to the first clamp means, for presenting a composite second digital signal.
Claim 2
Dependent Claim
197 words
A pulse converter circuit for converting a first digital signal compatible with a first logic family having first predetermined high and low logic levels and positive and negative slew rates, to a second digital signal compatible with a second logic family having second predetermined high and low logic levels and positive and negative slew rates, said circuit comprising: first means for receiving said first digital signal, and signals representative of the predetermined high and low logic levels and the positive and negative slew rates compatible with the second logic family; first voltage translator means for continuously detecting the logic state and state transitions of said first digital signal; slew rate adjustment means for establishing logic state transition rates in response to the predetermined positive and negative slew rate representative signals at the transition times detected by said voltage translator means; first clamp means for establishing the high and low logic levels of the second digital signal in response to the signals representative of the predetermined high and low logic levels, and the transition rates established by the slew rate adjustment means; and output means coupled to the first clamp means, for presenting a composite second digital signal.
Claim 3
Dependent Claim
25 words
A pulse converter circuit as in claim 1 wherein said first voltage translator means includes first differential amplifier means compatible with the first logic family.
Claim 4
Dependent Claim
155 words
A pulse converter circuit as in claim 2 wherein said slew rate adjustment means includes: first voltage to current converter means coupled to receive the voltage signal representative of the predetermined positive slew rate for generating a current representative thereof; second voltage to current converter means coupled to receive the voltage signal representative of the predetermined negative slew rate for generating a current representative thereof; second differential amplifier means responsive to the output signal of the first differential amplifier means for generating an output current transition for causing the logic state transition from the low state to the high state of the circuit to have the predetermined positive slew rate; third differential amplifier means responsive to the output signal of the first differential amplifier means for generating an output current transition for causing the logic state transition from the high state to the low state of the circuit to have the predetermined negative slew rate.
Claim 5
Dependent Claim
123 words
A pulse converter circuit as in claim 3 wherein: the output of second differential amplifier forms node I and the output of third differential amplifier forms node II; and said first clamp means includes: positive clamp means connected to node I and coupled to receive the signal representative of the predetermined high logic level for fixing the magnitude of the steady-state voltage on node I to the value of the signal representative of the predetermined high logic level; and negative clamp means connected to node II and coupled to receive the signal representative of the predetermined low logic level for fixing the magnitude of the steady-state voltage on node II to the value of the signal representative of the predetermined low logic level.
Claim 6
Dependent Claim
49 words
A pulse converter circuit as in claim 4 wherein said output means includes: transistor means coupled between nodes I and II; and bias means coupled between nodes I and II for maintaining a constant voltage separation between said nodes to maintain said transistor means biased in the active region.
Claim 7
Dependent Claim
77 words
A pulse converter circuit as in claim 5 wherein: said bias means maintains a preselected voltage difference between nodes I and II; said second differential amplifier means having a high and a low output current when said first digital signal is in its high and low logic state, respectively; and said third differential amplifier means having a high and a low output current when said first digital signal is in its low and high logic state, respectively.
Claim 8
Dependent Claim
42 words
A pulse converter circuit as in claim 6 wherein the positive and negative slew rates of the second digital signal result from the difference between the output currents of said second and third differential amplifiers and the parasitic capacitance of the circuit.
Claim 9
Dependent Claim
45 words
A pulse converter circuit as in claim 1 wherein: said first means also receives an output inhibit signal; and said circuit further comprises: second voltage translator means for detecting the inhibit signal and for inhibiting the output of said second digital signal during that period.
Claim 10
Dependent Claim
47 words
A pulse converter circuit as in claim 8 wherein said second voltage translator means includes: fourth differential amplifier means for detecting the inhibit period of the inhibit signal; and second clamp means for inhibiting the output by causing the output means to provide a floating output terminal.
Claim 11
Dependent Claim
58 words
A pulse converter circuit as in claim 4 wherein: said first means also receives an output inhibit signal; and said circuit further comprises: second voltage translator means for detecting the inhibit period of the inhibit signal and for inhibiting the output of said second digital signal during that period by inverting the voltages on nodes I and II.
Claim 12
Dependent Claim
82 words
A pulse converter circuit as in claim 10 wherein said second voltage translator means includes: fourth differential amplifier means coupled between the first means and nodes I and II for detecting the inhibit period and inverting the voltages on nodes I and II; and second clamp means for inhibiting the output by causing the output means to provide a floating output terminal by clamping nodes I and II to the predetermined low and high logic levels of the second digital family, respectively.
Claim 13
Independent Claim
141 words
A method of converting a first digital signal compatible with a first logic family to a second digital signal compatible with a second logic family having predetermined high and low logic levels and positive and negative slew rates, said method comprising the steps of: a. continuously monitoring the logic state and detecting the state transitions of said first digital signal; b. establishing logic state transition rates corresponding to the predetermined positive and negative slew rates at the detected state transition times of the first digital signal; c. translating the high and low logic state levels of the first digital signal to the predetermined high and low logic state levels of the second digital signal, respectively; and d. linking the predetermined high and low logic levels one to the other with the corresponding state transition rate to form the second digital signal.
Claim 14
Independent Claim
141 words
A method of converting a first digital signal compatible with a first logic family to a second digital signal compatible with a second logic family having predetermined high and low logic levels and positive and negative slew rates, said method comprising the steps of: a. continuously monitoring the logic state and detecting the state transitions of said first digital signal; b. establishing logic state transition rates corresponding to the predetermined positive and negative slew rates at the detected state transition times of the first digital signal; c. translating the high and low logic state levels of the first digital signal to the predetermined high and low logic state levels of the second digital signal, respectively; and d. linking the predetermined high and low logic levels one to the other with the corresponding state transition rate to form the second digital signal.
Claim 15
Dependent Claim
29 words
A method as in claim 12 wherein the transition rates of the first digital signal are at least as fast as the transition rates of the second digital signal.
Claim 16
Dependent Claim
21 words
A method as in claim 12 further comprising the step of inhibiting the conversion in response to a predetermined inhibit signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-03-25 | 1988-09-24 | 1989-03-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-03-25 | 1992-09-24 | 1993-03-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-03-25 | 1996-09-24 | 1997-03-26 | $7700.00 | Window Closed / Lapsed |