Patent US4506281A successfully refreshed from Google Patents.
US4506281A
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US
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GaAs semiconductor device
Assignee: Semiconductor Research Foundation
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Filing: 1981-08-24
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Granted: 1985-03-19
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Expires: 2001-08-24
Abstract
Abstract This invention relates to a GaAs semiconductor device and more particularly to a GaAs static induction transistor integrated circuit which operates at a very high speed. Gallium arsenide has the features that the mobility of electrons is higher than that in silicon and that the band structure has a direct gap. The mobility of electrons in gallium arsenide is several times as high as that in silicon; this is very suitable for the manufacture of a semiconductor device of high-speed operation. Further, since gallium arsenide has the direct gap, the electron-hole recombination rate is high and the minority carrier storage effect is extremely small. By causing the recombination at the direct gap, light emission can be achieved more efficiently. Accordingly, a light receiving and emitting semiconductor device can be obtained through the use of gallium arsenide. As the propagation velocity of light is very fast, signal transfer between semiconductor chips can be achieved at ultra-high speed. By combining this with the high mobility of electrons in gallium arsenide, an ultra-high speed logical operation device can be realized.
Inventors
- 👤 Jun-ichi Nishizawa
- 👤 Tadahiro Ohmi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 08:56
CPC Classifications
H; H10; H10D; H10D12/00; H10D84/00; H10D84/01; H10D84/02; H10D84/05; H10D89/00; H10D89/211; H10D89/213; H10D89/217; H10P; H10P14/00; H10P14/60; H10P14/66; H10P14/662
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
284 words
A GaAs semiconductor device, comprising: an n type GaAs layer of low resistivity; an n type intermediate GaAs layer of high resistivity overlying said n type layer; an n type GaAs surface layer of low resistivity overlying said n type intermediate layer; a first p type GaAs region of low resistivity having a through hole path therein, extending from the surface of said n type surface layer at least into said n type intermediate layer, surrounding a first portion of each of said n type surface layer and said n type intermediate layer and defining a continuous n type current path between said n type layer and said first portion of the n type surface layer; the first portion of said n type intermediate layer having such dimensions that the built-in voltage of the pn junction with the first p type region established a depletion layer therein to produce a potential barrier for electrons in said continuous n type current path without any external bias applied to said first p type region; a second p type GaAs region of low resistivity located in said n type intermediate layer in the neighborhood of said first p type region and sandwiching a second portion of said n type intermediate layer therebetween; the n type layer, the first portions of the n type intermediate layer and the n type surface layer and the first p type region constituting a source, a channel, a drain and a gate of an n channel static induction transistor; the second p type region, the second portion of the n type intermediate layer of the first p type region constituting an emitter, a base and a collector of a pnp bipolar transistor.
Claim 2
Dependent Claim
284 words
A GaAs semiconductor device, comprising: an n type GaAs layer of low resistivity; an n type intermediate GaAs layer of high resistivity overlying said n type layer; an n type GaAs surface layer of low resistivity overlying said n type intermediate layer; a first p type GaAs region of low resistivity having a through hole path therein, extending from the surface of said n type surface layer at least into said n type intermediate layer, surrounding a first portion of each of said n type surface layer and said n type intermediate layer and defining a continuous n type current path between said n type layer and said first portion of the n type surface layer; the first portion of said n type intermediate layer having such dimensions that the built-in voltage of the pn junction with the first p type region established a depletion layer therein to produce a potential barrier for electrons in said continuous n type current path without any external bias applied to said first p type region; a second p type GaAs region of low resistivity located in said n type intermediate layer in the neighborhood of said first p type region and sandwiching a second portion of said n type intermediate layer therebetween; the n type layer, the first portions of the n type intermediate layer and the n type surface layer and the first p type region constituting a source, a channel, a drain and a gate of an n channel static induction transistor; the second p type region, the second portion of the n type intermediate layer of the first p type region constituting an emitter, a base and a collector of a pnp bipolar transistor.
Claim 3
Dependent Claim
332 words
A GaAs semconductor device comprising: an n type layer of low resistivity overlying said n type layer of low resistivity; an n type GaAs surface layer of low resistivity overlying said n type intermediate layer; a first p type GaAs region of low resistivity having a through hole path therein, extending from the surface of said n type surface layer at least into said n type intermediate layer, surrounding a first portion of each of said n type surface layer and said n type intermediate layer and defining a continuous n type current path between said n type layer and said first portion of the n type surface layer; the first portion of said n type intermediate layer having such dimensions that the built-in voltage of the pn junction with the first p type region establishes a depletion layer therein to produce a potential barrier for electrons in said continuous n type current path without any external bias applied to said first p type region; and a second p type GaAs region of low resistivity located in said n type intermediate layer in the neighborhood of said first p type region and sandwiching a second portion of said n type intermediate layer therebetween; the n type layer, the first portions of the n type intermediate layer and the n type surface layer and the first p type region constituting a source, a channel, a drain and a gate of an n channel static induction transistor, the second p type region, the second portion of the n type intermediate layer and the first p type region constituting an emitter, a base and a collector of a pnp bipolar transistor; a photodiode for converting a light signal into an electrical signal, including a p type anode region electrically connected to at least one p type region and an n type cathode region located adjacent to and forming a pn junction with said anode region and adapted to be supplied with a positive bias voltage.
Claim 4
Dependent Claim
332 words
A GaAs semconductor device comprising: an n type layer of low resistivity overlying said n type layer of low resistivity; an n type GaAs surface layer of low resistivity overlying said n type intermediate layer; a first p type GaAs region of low resistivity having a through hole path therein, extending from the surface of said n type surface layer at least into said n type intermediate layer, surrounding a first portion of each of said n type surface layer and said n type intermediate layer and defining a continuous n type current path between said n type layer and said first portion of the n type surface layer; the first portion of said n type intermediate layer having such dimensions that the built-in voltage of the pn junction with the first p type region establishes a depletion layer therein to produce a potential barrier for electrons in said continuous n type current path without any external bias applied to said first p type region; and a second p type GaAs region of low resistivity located in said n type intermediate layer in the neighborhood of said first p type region and sandwiching a second portion of said n type intermediate layer therebetween; the n type layer, the first portions of the n type intermediate layer and the n type surface layer and the first p type region constituting a source, a channel, a drain and a gate of an n channel static induction transistor, the second p type region, the second portion of the n type intermediate layer and the first p type region constituting an emitter, a base and a collector of a pnp bipolar transistor; a photodiode for converting a light signal into an electrical signal, including a p type anode region electrically connected to at least one p type region and an n type cathode region located adjacent to and forming a pn junction with said anode region and adapted to be supplied with a positive bias voltage.
Claim 5
Dependent Claim
309 words
A GaAs semiconductor device, comprising: a n type GaAs layer of low resistivity; a n type intermediate GaAs layer of high resistivity overlying said n type layer; a n type GaAs surface layer of low resistivity overlying said n type intermediate layer; a first p type GaAs region of low resistivity having a through hole path therein, extending from the surface of said n type surface layer at least into said n type intermediate layer surrounding a first portion of each of said n type surface layer and said n type intermediate layer and defining a continuous n type current path between said n type layer and said first portion of the n type surface layer; the first portion of said n type intermediate layer having such dimensions that the built-in voltage of the pn junction with the first p type region establishes a depletion layer therein to produce a potential barrier for electrons in said continuous n type current path without any external bias applied to said first p type region, a second p type GaAs region of low resistivity located in said n type intermediate layer in the neighborhood of said first n type region and sandwiching a second portion of said n type intermediate layer therebetween; an insulated electrode structure formed on said second portion of the n type intermediate layer; the n type layer, the first portions of the n type intermediate layer and the n type surface layer and the first p type region constituting a source, a channel, a drain and a gate of an n channel static induction transistor, the second p type region, the second portion of the n type intermediate layer, the first p type region and the insulated electrode structure constituting a source, a channel, a drain and an insulated gate electrode of an insulated gate field effect transistor.
Claim 6
Dependent Claim
309 words
A GaAs semiconductor device, comprising: a n type GaAs layer of low resistivity; a n type intermediate GaAs layer of high resistivity overlying said n type layer; a n type GaAs surface layer of low resistivity overlying said n type intermediate layer; a first p type GaAs region of low resistivity having a through hole path therein, extending from the surface of said n type surface layer at least into said n type intermediate layer surrounding a first portion of each of said n type surface layer and said n type intermediate layer and defining a continuous n type current path between said n type layer and said first portion of the n type surface layer; the first portion of said n type intermediate layer having such dimensions that the built-in voltage of the pn junction with the first p type region establishes a depletion layer therein to produce a potential barrier for electrons in said continuous n type current path without any external bias applied to said first p type region, a second p type GaAs region of low resistivity located in said n type intermediate layer in the neighborhood of said first n type region and sandwiching a second portion of said n type intermediate layer therebetween; an insulated electrode structure formed on said second portion of the n type intermediate layer; the n type layer, the first portions of the n type intermediate layer and the n type surface layer and the first p type region constituting a source, a channel, a drain and a gate of an n channel static induction transistor, the second p type region, the second portion of the n type intermediate layer, the first p type region and the insulated electrode structure constituting a source, a channel, a drain and an insulated gate electrode of an insulated gate field effect transistor.
Claim 7
Dependent Claim
363 words
A GaAs semiconductor device, comprising: an n type GaAs layer of low resistivity; an n type intermediate GaAs layer of high resistivity overlying said n type layer; an n type GaAs surface layer of low resistivity overlying said n type intermediate layer; a first p type GaAs region of low resistivity having a through hole path therein, extending from the surface of said n type surface layer at least into said n type intermediate layer, surrounding a first portion of each of said n type surface layer and said n type intermediate layer and defining a continuous n type current path between said n type layer and said first portion of the n type surface layer; the first portion of said n type intermediate layer having such dimensions that the built-in voltage of the pn junction with the first p type region establishes a depletion layer therein to produce a potential barrier for electrons in said continuous n type current path without any external bias applied to said first p type region, a second p type GaAs region of low resistivity located in said n type intermediate layer in the neighborhood of said first n type region and sandwiching a second portion of said n type intermediate layer therebetween; an insulated electrode structure formed on said second portion of the n type intermediate layer; the n type layer, the first portions of the n type intermediate layer and the n type surface layer and the first p type region constituting a source, a channel, a drain and a gate of an n channel static induction transistor, the second p type region, the second portions of the n type intermediate layer, the first p type region and the insulated electrode structure constituting a source, a channel, a drain and an insulated gate electrode of an insulated gate field effect transistor; and a photodiode for converting a light into an electrical signal, including a p type anode region electrically connected to at least one p type region and an n type cathode region located adjacent to and forming a pn junction with said anode region and adapted to be supplied with a positive bias voltage.
Claim 8
Dependent Claim
363 words
A GaAs semiconductor device, comprising: an n type GaAs layer of low resistivity; an n type intermediate GaAs layer of high resistivity overlying said n type layer; an n type GaAs surface layer of low resistivity overlying said n type intermediate layer; a first p type GaAs region of low resistivity having a through hole path therein, extending from the surface of said n type surface layer at least into said n type intermediate layer, surrounding a first portion of each of said n type surface layer and said n type intermediate layer and defining a continuous n type current path between said n type layer and said first portion of the n type surface layer; the first portion of said n type intermediate layer having such dimensions that the built-in voltage of the pn junction with the first p type region establishes a depletion layer therein to produce a potential barrier for electrons in said continuous n type current path without any external bias applied to said first p type region, a second p type GaAs region of low resistivity located in said n type intermediate layer in the neighborhood of said first n type region and sandwiching a second portion of said n type intermediate layer therebetween; an insulated electrode structure formed on said second portion of the n type intermediate layer; the n type layer, the first portions of the n type intermediate layer and the n type surface layer and the first p type region constituting a source, a channel, a drain and a gate of an n channel static induction transistor, the second p type region, the second portions of the n type intermediate layer, the first p type region and the insulated electrode structure constituting a source, a channel, a drain and an insulated gate electrode of an insulated gate field effect transistor; and a photodiode for converting a light into an electrical signal, including a p type anode region electrically connected to at least one p type region and an n type cathode region located adjacent to and forming a pn junction with said anode region and adapted to be supplied with a positive bias voltage.
Claim 9
Dependent Claim
306 words
A GaAs semiconductor device, comprising: an n type GaAs layer of low resistivity; an n type intermediate GaAs layer of high resistivity overlying said n type layer; an n type GaAs surface layer of low resistivity overlying said n type intermediate layer; a first p type GaAs region of low resistivity having a through hole path therein, extending from the surface of said n type surface layer at least into said n type intermediate layer, surrounding a first portion of each of said n type surface layer and said n type intermediate layer and defining a continuous n type current path between said n type layer and said first portion of the n type surface layer; the first portion of said n type intermediate layer having such dimensions that the built-in voltage of the pn junction with the first p type region establishes a depletion layer therein to produce a potential barrier for electrons in said continuous n type current path without any external bias applied to said first p type region, a second p type GaAs region of low resistivity located in said n type intermediate layer in the neighborhood of said first p type region and sandwiching a second portion of said n type intermediate layer therebetween; the n type layer, the first portions of the n type intermediate layer and the n type surface layer and the first p type region constituting a source, a channel, a drain and a gate of an n channel statis induction transistor, the second p type region, the second portion of the n type intermediate layer and the first p type region constituting an emitter, a base and a collector of a pnp bipolar transistor; and a semi-insulating GaAs region formed by ion bombardment and surrounding said n channel static induction transistor and said bipolar transistor therein.
Claim 10
Dependent Claim
306 words
A GaAs semiconductor device, comprising: an n type GaAs layer of low resistivity; an n type intermediate GaAs layer of high resistivity overlying said n type layer; an n type GaAs surface layer of low resistivity overlying said n type intermediate layer; a first p type GaAs region of low resistivity having a through hole path therein, extending from the surface of said n type surface layer at least into said n type intermediate layer, surrounding a first portion of each of said n type surface layer and said n type intermediate layer and defining a continuous n type current path between said n type layer and said first portion of the n type surface layer; the first portion of said n type intermediate layer having such dimensions that the built-in voltage of the pn junction with the first p type region establishes a depletion layer therein to produce a potential barrier for electrons in said continuous n type current path without any external bias applied to said first p type region, a second p type GaAs region of low resistivity located in said n type intermediate layer in the neighborhood of said first p type region and sandwiching a second portion of said n type intermediate layer therebetween; the n type layer, the first portions of the n type intermediate layer and the n type surface layer and the first p type region constituting a source, a channel, a drain and a gate of an n channel statis induction transistor, the second p type region, the second portion of the n type intermediate layer and the first p type region constituting an emitter, a base and a collector of a pnp bipolar transistor; and a semi-insulating GaAs region formed by ion bombardment and surrounding said n channel static induction transistor and said bipolar transistor therein.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-03-18 | 1988-09-17 | 1989-03-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-03-18 | 1992-09-17 | 1993-03-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-03-18 | 1996-09-17 | 1997-03-19 | $7700.00 | Window Closed / Lapsed |