Patent US4430496A successfully refreshed from Google Patents.
Patent US4506201A successfully refreshed from Google Patents.
US4506201A
Expired / Lapsed
US
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Microprocessor controlled pulse motor
Assignee: Toshiba Corp
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Filing: 1983-05-09
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Granted: 1985-03-19
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Expires: 2003-05-09
Abstract
Abstract A pulse motor control device is provided with a microprocessor for presetting time data in a counter to determine a rotating speed of a pulse motor according to an interrupt signal, in which an overflow pulse from the counter is supplied as an interrupt signal to the microprocessor and is also applied as a phase data changing signal, which determines the period of the phase data, to a motor control circuit. A gate is provided at a prestage of the interrupt terminal of the microprocessor. When the pulse motor is driven at a constant speed, the gate is disabled to prohibit the interrupt signal from being applied to the microprocessor.
Inventors
- 👤 Yukio Tsuneki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 18:57
CPC Classifications
H; H02; H02P; H02P8/00; H02P8/40; H02P23/00; H02P23/0077
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
146 words
A microprocessor controlled pulse motor comprising: a microprocessor having first and second operation modes, the first operation mode executing a program according to an applied interrupt signal and for producing time data according to the program executed, and the second operation mode producing no output, the periods of the first and second operation modes being determined by the microprocessor; counter means for producing a pulse signal having a period which is varied according to the time data in the first operation mode and which is constant in the second operation mode which in the first operation mode supplies an interrupt signal to said microprocessor in synchronism with production of said pulse signal, and which in the second operation mode inhibits said interrupt signal from being supplied to said microprocessor; and motor control means for controlling the rotation of the pulse motor according to said pulse signal.
Claim 2
Dependent Claim
146 words
A microprocessor controlled pulse motor comprising: a microprocessor having first and second operation modes, the first operation mode executing a program according to an applied interrupt signal and for producing time data according to the program executed, and the second operation mode producing no output, the periods of the first and second operation modes being determined by the microprocessor; counter means for producing a pulse signal having a period which is varied according to the time data in the first operation mode and which is constant in the second operation mode which in the first operation mode supplies an interrupt signal to said microprocessor in synchronism with production of said pulse signal, and which in the second operation mode inhibits said interrupt signal from being supplied to said microprocessor; and motor control means for controlling the rotation of the pulse motor according to said pulse signal.
Claim 3
Dependent Claim
41 words
A pulse motor control device according to claim 1, in which the time data produced by said microprocessor is preset in said counter means, and said counter means is counted down and produces an overflow pulse when the count reaches 0.
Claim 4
Dependent Claim
35 words
A pulse motor control device according to claim 2, in which said microprocessor produces time data which is gradually increased in an acceleration mode of the pulse motor and gradually decreased in a deceleration mode.
Claim 5
Dependent Claim
52 words
A pulse motor control device according to claim 3, in which said counter means is set in a first operation mode at the time of acceleration and deceleration of the pulse motor, and is set in a second operation mode during the course of the constant speed control of the pulse motor.
Claim 6
Dependent Claim
118 words
A pulse motor control device according to claim 4, in which said counter means has first and second counters in which the time data produced by said microprocessor is stored, in which said first counter counts down at the time of acceleration and deceleration of the pulse motor, and, when its count reaches 0, produces an overflow pulse, and said second counter counts down during the course of the constant speed control of the pulse motor while producing an operation signal, the overflow pulse derived from said first counter is supplied to said motor control means and also to an interrupt terminal of said microprocessor through a gate disabled by the operation signal produced from said second counter.
Claim 7
Dependent Claim
54 words
A pulse motor control device according to claim 5, in which the preset time data in said first counter is increased and decreased for every overflow during the acceleration and deceleration of the pulse motor, while being kept at a constant value during the course of the constant speed control of the pulse motor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-03-18 | 1988-09-17 | 1989-03-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-03-18 | 1992-09-17 | 1993-03-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-03-18 | 1996-09-17 | 1997-03-19 | $7700.00 | Window Closed / Lapsed |