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Wide band frequency phase locked loop frequency synthesizer

Assignee: Thales SA
•
Filing: 1982-07-09
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Granted: 1985-03-12
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Expires: 2002-07-09
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Abstract

Abstract The synthesizer comprises a single phase loop formed by two stages of a frequency divider inserted between the voltage controlled oscillator and the phase comparator. The synthesized frequency is taken from the connection between the two stages, which allows a frequency range to be obtained extending over a wide band with a voltage controlled oscillator itself having a small relative band width.

Inventors

  • 👤 Eric Plouviez

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-04 14:52
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/16; H03L7/18; H03L7/183

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 111 words
A wide band frequency synthesizer, of the type comprising a voltage controlled oscillator, and a phase control loop, comprising a divider for dividing by an integer number the frequency of the signal supplied by the oscillator, a phase comparator for comparing the signal supplied by the divider with a constant reference frequency signal and delivering an error signal measuring the frequency and phase difference between the compared signals, and means for controlling the oscillator by means of this error signal, wherein the divider comprises first and second serially coupled divider means having programmable division ranks and the synthesized signal being obtained at the connection between the first and second divider means.
Claim 2
Dependent Claim 111 words
A wide band frequency synthesizer, of the type comprising a voltage controlled oscillator, and a phase control loop, comprising a divider for dividing by an integer number the frequency of the signal supplied by the oscillator, a phase comparator for comparing the signal supplied by the divider with a constant reference frequency signal and delivering an error signal measuring the frequency and phase difference between the compared signals, and means for controlling the oscillator by means of this error signal, wherein the divider comprises first and second serially coupled divider means having programmable division ranks and the synthesized signal being obtained at the connection between the first and second divider means.
Claim 3
Dependent Claim 52 words
The synthesizer as claimed in claim 1, wherein the means for controlling the oscillator comprises a filter and an amplifier for obtaining a control voltage which acts with feedback on the oscillator with an open loop gain of the phase control loop substantially constant over all the frequencies delivered by the synthesizer.
Claim 4
Dependent Claim 23 words
The synthesizer as claimed in claim 2, wherein the constant reference frequency is applied to the phase comparator through a third divider means.
Claim 5
Dependent Claim 57 words
The synthesizer as claimed in claim 3, wherein the constant reference frequency is substantially equal to 64 kHz and the second divider means may be programmed for a division rank going from 1 to 32; the synthesizer in this case possibly supplying the first 32 multiple frequencies of 64 kHz extending over a range of 5 octaves.
Claim 6
Dependent Claim 32 words
The synthesizer as claimed in claim 4, wherein the oscillator is tunable between 6.9 and 10 MHz and the first divider means is programmable to a division rank from 2 to 40.

References Cited (Backward Citations)

FR1473202A Cited
US3828271A Cited
US4002995A Cited
US4078213A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1988-03-11 1988-09-10 1989-03-12 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1992-03-11 1992-09-10 1993-03-12 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1996-03-11 1996-09-10 1997-03-12 $7700.00 Window Closed / Lapsed

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