Patent US2816705A successfully refreshed from Google Patents.
Patent US4504784A successfully refreshed from Google Patents.
US4504784A
Expired / Lapsed
US
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Method of electrically testing a packaging structure having N interconnected integrated circuit chips
Assignee: International Business Machines Corp
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Filing: 1983-07-29
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Granted: 1985-03-12
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Expires: 2003-07-29
Abstract
Abstract Design rules and test structure are used to implement machine designs to thereby obviate during testing the need for mechanical probing of the chip, multichip module, card or board at a higher level of package. The design rules and test structure also provide a means of restricting the size of logic partitions on large logical structures to facilitate test pattern generation. A test mechanism is available on every chip to be packaged to drive test data on all chip outputs and observe test data on all chip inputs, independent of the logic function performed by the chip. A control mechanism is also provided to allow a chip to either perform its intended function or to act as a testing mechanism during package test. It is intended that the test mechanism built into every chip will be used in place of mechanical probes to perform a chip-in-place test and interchip wiring test of the package. The intent of the design rules is to design chips such that each chip can be "isolated" for testing purposes through the pins (or other contacts) of a higher level package containing such chips. It is also required that the "Level Sensitive Scan Design" (LSSD) discipline, or rules, be followed for each chip and for the package clock distribution network. Further, the LSSD Rules which ensures the capability of scanning data into and out of the package SRLs (shift register latches) must be satisfied for the total package.
Inventors
- 👤 Prabhakar Goel
- 👤 Maurice T. McMahon
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 08:58
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318544; G01R31/31855
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
381 words
A method for performing an electrical test on a packaging structure containing n interconnected integrated circuit chips, each of said n integrated circuit chips including test circuit means, said test circuit means including scan-in scan-out circuit means, said scan-in scan-out circuit means including shift register latch circuit means, said test circuit means of each of said n integrated circuit chips further including control circuit means, said control circuit means cooperating with said scan-in scan-out circuit means of each of said n interconnected integrated circuit chips, said control circuit means being controllable to place all but any selected one of said n interconnected integrated circuit chips in a "test" mode, said selected one of said n interconnected integrated circuit chips being a chip under test, said packaging structure being characterized in that electrical contact to said packaging structure and each of said n interconnected integrated circuit chips is only provided through a plurality of accessible packaging contacts, said packaging structure including wiring for interconnecting said n interconnected integrated circuit chips one with another and said accessible packaging contacts, said wiring of said packaging structure including wiring for connecting said scan-in scan-out circuit means of said test circuit means of each of said n integrated circuit chips into a single packaging structure scan-in scan-out circuit means, said method determining the electrical integrity of any predetermined one of said plurality of integrated circuit chips and including in the order recited the following steps: (1) placing a binary value in said packaging structure scan-in scan-out circuit means; (2) placing each chip of said n interconnected integrated circuit chips, except said any selected one of said n integrated circuit chips, in a "test mode", whereby said selected one of said n interconnected integrated circuit chips is a "chip under test (CUT)"; (3) employing at least the binary value placed in said packaging structure scan-in-scan-out circuit means impress a binary value input on the integrated circuit chip under test; and (4) employing at least the packaging structure scan-in-scan-out circuit means obtain and examine a binary output from said chip under test to determine the electrical integrity of said chip under test, wherein the term electrical integrity of said chip under test is defined as determining whether or not said integrated circuit chip under test is electrically defective.
Claim 2
Independent Claim
381 words
A method for performing an electrical test on a packaging structure containing n interconnected integrated circuit chips, each of said n integrated circuit chips including test circuit means, said test circuit means including scan-in scan-out circuit means, said scan-in scan-out circuit means including shift register latch circuit means, said test circuit means of each of said n integrated circuit chips further including control circuit means, said control circuit means cooperating with said scan-in scan-out circuit means of each of said n interconnected integrated circuit chips, said control circuit means being controllable to place all but any selected one of said n interconnected integrated circuit chips in a "test" mode, said selected one of said n interconnected integrated circuit chips being a chip under test, said packaging structure being characterized in that electrical contact to said packaging structure and each of said n interconnected integrated circuit chips is only provided through a plurality of accessible packaging contacts, said packaging structure including wiring for interconnecting said n interconnected integrated circuit chips one with another and said accessible packaging contacts, said wiring of said packaging structure including wiring for connecting said scan-in scan-out circuit means of said test circuit means of each of said n integrated circuit chips into a single packaging structure scan-in scan-out circuit means, said method determining the electrical integrity of any predetermined one of said plurality of integrated circuit chips and including in the order recited the following steps: (1) placing a binary value in said packaging structure scan-in scan-out circuit means; (2) placing each chip of said n interconnected integrated circuit chips, except said any selected one of said n integrated circuit chips, in a "test mode", whereby said selected one of said n interconnected integrated circuit chips is a "chip under test (CUT)"; (3) employing at least the binary value placed in said packaging structure scan-in-scan-out circuit means impress a binary value input on the integrated circuit chip under test; and (4) employing at least the packaging structure scan-in-scan-out circuit means obtain and examine a binary output from said chip under test to determine the electrical integrity of said chip under test, wherein the term electrical integrity of said chip under test is defined as determining whether or not said integrated circuit chip under test is electrically defective.
Claim 3
Dependent Claim
243 words
A method for performing an electrical test on a packaging structure containing n interconnected integrated circuit chips, each of said n integrated circuit chips including test circuit means, said test circuit means including scan-in scan-out circuit means, said scan-in scan-out circuit means including shift register latch circuit means, said test circuit means of each of said n integrated circuit chips further including control circuit means, said control circuit means cooperating with said scan-in scan-out circuit means of each of said n interconnected integrated circuit chips, said control circuit means being controllable to place all but any selected one of said n interconnected integrated circuit chips in a "test" mode, said selected one of said n interconnected integrated circuit chips being a chip under test, said packaging structure being characterized in that electrical contact to said packaging structure and each of said n interconnected integrated circuit chips is only provided through a plurality of accessible packaging contacts, said packaging structure including wiring for interconnecting said n interconnected integrated circuit chips one with another and said accessible packaging contacts, said wiring of said packaging structure including wiring for connecting said scan-in scan-out circuit means of said test circuit means of each of said n integrated circuit chips into a packaging structure scan-in-scan-out circuit means, wherein said method, as recited in claim 1, including said four steps, is repeated n times to respectively determine the electrical integrity of each of said n interconnected integrated circuit chips.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-03-11 | 1988-09-10 | 1989-03-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-03-11 | 1992-09-10 | 1993-03-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-03-11 | 1996-09-10 | 1997-03-12 | $7700.00 | Window Closed / Lapsed |