Consecutive identical digit suppression system in a digital communication system

Claim 2

A consecutive identical digit suppression bit insertion system in a digital communication system comprising; an input terminal for receiving an input signal, rate converting means coupled to the input terminal for converting the transmission bit rate of the input signal to (m+1)/m times the rate of the input signal where m is the integer number of input bits between insertion bits, means coupled to the converting means for receiving the converted signal and inserting an additional bit after the m th bit, the insertion bit comprising the complement of the k th bit previous to the insertion bit where k is an integer satisfying 1<k<m and the insertion bit has the same bit rate as the m converted bits, and an output terminal coupled to the inserting means for providing an encoded signal with m bits of input signal and one inserted bit.

Claim 3

A consecutive identical digit suppression system according to claim 1, wherein the value k is 1.

Claim 4

A consecutive identical digit suppression system according to claim 1, wherein the value of m is less than 12.

Claim 5

A consecutive identical digit suppression system in a digital communication system comprising: (a) a first input terminal for receiving input digital data which data has a dummy bit position every m bits where m is an integer and the dummy bit reserves the bit position for an insertion bit, (b) a second input terminal for receiving a clock signal having the same bit rate as the bit rate of the input digital data, (c) an output terminal for providing encoded output data, (d) first shift register means coupled to the first and second input terminals for receiving and shifting each bit of the input digital data through k bit positions where k is an integer and for providing register outputs Q and Q, where Q has the value of that input bit which has been shifted entirely through the k positions of the shift register and Q is a complement of Q, (e) a divider coupled to said second input terminal for dividing said clock signal and thereby providing a divided pulse C M having a period (m+1) times the period of said clock signal, (f) first and second AND circuit means coupled to said pulse C M wherein the first AND means is also coupled to said output Q for providing an output R 1 =QC M and the second AND means is coupled to said output Q for providing an output S 1 =QC M , (g) second and third shift register means coupled to said first and second AND circuit means for shifting the outputs (S 1 , and R 1 ) of said AND circuit means by (k+1) bit positions to provide the outputs S 2 and R 2 from the inputs S 1 and R 1 respectively, and (h) a flip-flop, which is clocked according to said received clock signal, switched according to said output Q, set by the signal S 2 , and reset by the signal R 2 to provide an output signal to said output terminal, so that a complement of k th bit previous to said dummy bit position is inserted in said dummy bit position in the input data wherein the output of said flip-flop is applied to said output terminal.

Claim 6

A consecutive identical digit suppression system in a digital communication system comprising: (a) a first input terminal for receiving input digital data which data has a dummy bit position every m bits where m is an integer and the dummy bit reserves the bit position for an insertion bit, (b) a second input terminal for receiving a clock signal having the same bit rate as the bit rate of the input digital data, (c) an output terminal for providing encoded output data, (d) first shift register means coupled to the first and second input terminals for receiving and shifting each bit of the input digital data through k bit positions where k is an integer and for providing register outputs Q and Q, where Q has the value of that input bit which has been shifted entirely through the k positions of the shift register and Q is a complement of Q, (e) a divider coupled to said second input terminal for dividing said clock signal and thereby providing a divided pulse C M having a period (m+1) times the period of said clock signal, (f) first and second AND circuit means coupled to said pulse C M wherein the first AND means is also coupled to said output Q for providing an output R 1 =QC M and the second AND means is coupled to said output Q for providing an output S 1 =QC M , (g) second and third shift register means coupled to said first and second AND circuit means for shifting the outputs (S 1 , and R 1 ) of said AND circuit means by (k+1) bit positions to provide the outputs S 2 and R 2 from the inputs S 1 and R 1 respectively, and (h) a flip-flop, which is clocked according to said received clock signal, switched according to said output Q, set by the signal S 2 , and reset by the signal R 2 to provide an output signal to said output terminal, so that a complement of k th bit previous to said dummy bit position is inserted in said dummy bit position in the input data wherein the output of said flip-flop is applied to said output terminal.

Claim 7

A consecutive identical digit suppression system according to claim 4, wherein said value of k is 1.

Claim 8

A consecutive identical digit suppression system in a digital communication system comprising: (a) a first input terminal for receiving input digital data which data has a dummy bit position every m bits where m is an integer and the dummy bit reserves the bit position for an insertion bit, (b) a second input terminal for receiving a clock signal having the same bit rate as the bit rate of the input digital data, (c) an output terminal for providing encoded output data, (d) shift register means coupled to the first input terminal for receiving and delaying the input signal by k+1 bit positions and providing an output signal Q 2 and an output signal Q 1 which is k bits previous to said Q 2 , (e) a pulse divider coupled to the second input terminal for providing an output pulse C 1 which has a period m+1 times the period of said clock signal, (f) an exclusive-OR circuit means for providing an output A which is an exclusive-OR output between said Q 2 and Q 1 at the timing that said output C 1 of said pulse divider exists, (g) delay means coupled to said shift register means for delaying the output of said shift register means to provide an output Q wherein Q is a delayed representation of said Q 2 , and (h) logic means for providing a signal satisfying QAC.sub.2 +QAC.sub.2 +QAC.sub.2 so that a complement of k th bit previous to the dummy bit position is inserted for every m bit positions of input data to provide output to said output terminal.

Claim 9

A consecutive identical digit suppression system in a digital communication system comprising: (a) a first input terminal for receiving input digital data which data has a dummy bit position every m bits where m is an integer and the dummy bit reserves the bit position for an insertion bit, (b) a second input terminal for receiving a clock signal having the same bit rate as the bit rate of the input digital data, (c) an output terminal for providing encoded output data, (d) shift register means coupled to the first input terminal for receiving and delaying the input signal by k+1 bit positions and providing an output signal Q 2 and an output signal Q 1 which is k bits previous to said Q 2 , (e) a pulse divider coupled to the second input terminal for providing an output pulse C 1 which has a period m+1 times the period of said clock signal, (f) an exclusive-OR circuit means for providing an output A which is an exclusive-OR output between said Q 2 and Q 1 at the timing that said output C 1 of said pulse divider exists, (g) delay means coupled to said shift register means for delaying the output of said shift register means to provide an output Q wherein Q is a delayed representation of said Q 2 , and (h) logic means for providing a signal satisfying QAC.sub.2 +QAC.sub.2 +QAC.sub.2 so that a complement of k th bit previous to the dummy bit position is inserted for every m bit positions of input data to provide output to said output terminal.

Claim 10

A consecutive identical digit suppression system according to claim 6, wherein the value k is 1.

Claim 11

A consecutive identical digit suppression system in a digital communication system comprising: (a) a first input terminal for receiving an input signal having a dummy bit position for every m bits where m is an integer and the dummy bit reserves the bit position for an insertion bit, (b) a second input terminal for receiving a clock signal having the same bit rate as the bit rate of the input signal, (c) an output terminal for providing encoded output data, (d) a serial-parallel converter coupled to said first and second input terminals for receiving and converting a serial signal on said input terminal to a parallel signal, (e) a complement generator having an exclusive-OR circuit for providing an exclusive-OR logic between the m'th output of said serial-parallel converter and k'th output of said serial-parallel converter thereby providing an exclusive-OR output signal Q EX , where m is an integer and k is an integer satisfying 1≦k≦m-1, (f) a logic circuit for switching the m'th output of said serial-parallel converter according to the exclusive-OR output signal Q EX of said exclusive-OR circuit, and (g) a parallel-serial converter receiving the first through the m'th outputs of said serial-parallel converter, and the output of said logic circuit to convert those input signals to a serial form to provide an output signal to said output terminal.

Claim 12

A consecutive identical digit suppression system in a digital communication system comprising: (a) a first input terminal for receiving an input signal having a dummy bit position for every m bits where m is an integer and the dummy bit reserves the bit position for an insertion bit, (b) a second input terminal for receiving a clock signal having the same bit rate as the bit rate of the input signal, (c) an output terminal for providing encoded output data, (d) a serial-parallel converter coupled to said first and second input terminals for receiving and converting a serial signal on said input terminal to a parallel signal, (e) a complement generator having an exclusive-OR circuit for providing an exclusive-OR logic between the m'th output of said serial-parallel converter and k'th output of said serial-parallel converter thereby providing an exclusive-OR output signal Q EX , where m is an integer and k is an integer satisfying 1≦k≦m-1, (f) a logic circuit for switching the m'th output of said serial-parallel converter according to the exclusive-OR output signal Q EX of said exclusive-OR circuit, and (g) a parallel-serial converter receiving the first through the m'th outputs of said serial-parallel converter, and the output of said logic circuit to convert those input signals to a serial form to provide an output signal to said output terminal.

Claim 13

A consecutive identical digit suppression system according to claim 8, wherein the value k is 1.