US4500801A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Self-powered nonregenerative fast gate turn-off FET
Assignee: Eaton Corp
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Filing: 1982-06-21
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Granted: 1985-02-19
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Expires: 2002-06-21
Abstract
Abstract A fast turn-off FET circuit is provided by a bipolar transistor in the gate circuit of the FET. The bipolar transistor is driven into conduction by residual charge in the gate to source capacitance of the FET upon turn-off of the latter due to removal of gate drive. Conduction of the bipolar transistor provides faster discharge therethrough of the FET gate, whereby to facilitate faster FET turn-off without reverse gating current and its attendant auxiliary power supply.
Inventors
- 👤 William J. Janutka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 20:50
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/04; H03K17/041; H03K17/0412; H03K17/04123
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
174 words
A fast turn-off FET circuit having drain, source and gate terminals, comprising; an enhancement mode FET having a drain connected to said drain terminal, a source connected to said source terminal, and a gate operatively coupled to said gate terminal; nonregenerative switch means comprising transistor means connected to said FET gate and source and driven into conduction by residual stored charge in the gate to source capacitance of said FET upon turn-off of the latter due to removal of gate drive, such that conduction of said switch means provides faster discharge therethrough of said FET gate, whereby to facilitate faster FET turn-off; gate biasing voltage source means for supplying gate drive to said gate terminal for carrying gate drive to said FET gate; wherein said transistor means comprises auxiliary FET means connected between said gate of said first mentioned FET and said source of said first mentioned FET, and biased OFF in response to gate drive to said first mentioned FET to prevent draining of said gate drive away from said first mentioned FET.
Claim 2
Dependent Claim
174 words
A fast turn-off FET circuit having drain, source and gate terminals, comprising; an enhancement mode FET having a drain connected to said drain terminal, a source connected to said source terminal, and a gate operatively coupled to said gate terminal; nonregenerative switch means comprising transistor means connected to said FET gate and source and driven into conduction by residual stored charge in the gate to source capacitance of said FET upon turn-off of the latter due to removal of gate drive, such that conduction of said switch means provides faster discharge therethrough of said FET gate, whereby to facilitate faster FET turn-off; gate biasing voltage source means for supplying gate drive to said gate terminal for carrying gate drive to said FET gate; wherein said transistor means comprises auxiliary FET means connected between said gate of said first mentioned FET and said source of said first mentioned FET, and biased OFF in response to gate drive to said first mentioned FET to prevent draining of said gate drive away from said first mentioned FET.
Claim 3
Dependent Claim
53 words
The invention according to claim 1 wherein said auxiliary FET means has one of its source and drain connected to said gate of said first mentioned FET, and the other of its source and drain connected to said source of said first mentioned FET, and has a gate connected to said gate terminal.
Claim 4
Dependent Claim
130 words
The invention according to claim 2 comprising a diode connected between said gate terminal and said first mentioned FET gate, said auxiliary FET means being connected to a node connecting said gate terminal and said diode, and said one of said source and drain of said auxiliary FET means being connected between said diode and said first mentioned FET gate, said diode being forward biased in response to gate drive to pass gate drive therethrough to drive said first mentioned FET gate, said diode being reverse biased in response to gate to source capacitance of said first mentioned FET upon removal of gate drive whereby to block current flow therethrough between said FET gate and said auxiliary FET means gate and insure biasing of said auxiliary FET means into conduction.
Claim 5
Dependent Claim
65 words
The invention according to claim 3 comprising resistor means connected between said gate of said auxiliary FET means and said other of said source and drain of said auxiliary FET means, of sufficient resistance to prevent significant diversion of gate drive from said gate terminal to said first mentioned FET source, and to provide a return path for biasing said auxiliary FET means into conduction.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-02-19 | 1988-08-20 | 1989-02-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-02-19 | 1992-08-20 | 1993-02-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-02-19 | 1996-08-20 | 1997-02-19 | $7700.00 | Window Closed / Lapsed |