Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
114 words
A counter circuit adapted to counting high frequency pulses and to being read while counting said pulses, comprising a plurality of pulse counting stages of increasing numerical significance with the lower significance stages connected as a synchronous counter and the higher significance stages connected as a ripple counter, early count signal means for applying a count signal to the ripple counter during each count cycle of the synchronous counter at an instant which is early relative to the synchronous counter cycling from its full count to its empty count, and read means including read timing means connected to read the state of the ripple counter regularly at a predetermined state of the synchronous counter.
Claim 2
Dependent Claim
114 words
A counter circuit adapted to counting high frequency pulses and to being read while counting said pulses, comprising a plurality of pulse counting stages of increasing numerical significance with the lower significance stages connected as a synchronous counter and the higher significance stages connected as a ripple counter, early count signal means for applying a count signal to the ripple counter during each count cycle of the synchronous counter at an instant which is early relative to the synchronous counter cycling from its full count to its empty count, and read means including read timing means connected to read the state of the ripple counter regularly at a predetermined state of the synchronous counter.
Claim 3
Dependent Claim
66 words
A counter circuit according to claim 1, wherein the number of stages in the synchronous counter is established so that the period separating two sucessive applications of said count signal to the ripple counter at the maximum frequency of the input pulses, is greater than the maximum length of time required for a count to ripple through the ripple counter in response to said count signal.
Claim 4
Dependent Claim
46 words
A counter circuit according to claim 1, wherein said early count signal means comprise means for detecting the passage of a predetermined state in the synchronous counter and for changing the state of the least significant stage of the ripple counter in response to said detection.
Claim 5
Dependent Claim
22 words
A counter circuit according to claim 1, wherein said read timing means include means for decoding the state of said synchronous counter.
Claim 6
Dependent Claim
29 words
A counter circuit according to claim 4, wherein said read timing means reads said ripple counter when the synchronous counter overflows from a full count to an empty count.
Claim 7
Dependent Claim
32 words
A counter circuit according to claim 1, wherein said read means include a first read register connected to read the stages of the ripple counter in response to said read timing means.
Claim 8
Dependent Claim
38 words
A counter circuit according to claim 6, wherein said read means include a second read register connected to read the stages of the synchronous counter in response to a read counter command being applied to the counter cicuit.
Claim 9
Dependent Claim
58 words
A counter circuit according to claim 7, including a first memory for recording the state of said first and second registers on receipt of a read counter command corresponding to a start count command, and a second memory for recording the state of the registers on receipt of a read counter command corresponding to an end count command.
Claim 10
Dependent Claim
53 words
A counter circuit according to claim 2, wherein said read means include a read register and wherein said read timing means and said read register are connected to read the state of the ripple counter in response to the pulses that correspond to switching of the least significant stage of the ripple counter.
Claim 11
Dependent Claim
87 words
A counter circuit according to claim 9, wherein said early count signal means comprise means for detecting a first change of state in the synchronous counter and for causing the ripple counter to change state in response to said detection, and wherein the read timing means comprise means for detecting a second change of state in the synchronous counter following the first change of state and for causing the contents of the ripple counter to be read by said read register in response to said second detection.
Claim 12
Dependent Claim
54 words
A counter circuit according to claim 10, wherein said second change of state corresponds to the two said synchronous counter overflows from the full count state, and wherein said first change of state corresponds to the most significant stage of the synchronous counter changing from an empty count state to a full count state.
Claim 13
Dependent Claim
48 words
A counter circuit according to claim 6, 7 or 9, including means for memorizing the contents of the ripple counter read register in response to a read counter command, and means for locking the read register during the time required for data transfer to said means for memorizing.