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US4497685A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Small area high value resistor with greatly reduced parasitic capacitance
Assignee: Newport Fab LLC
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Filing: 1983-10-24
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Granted: 1985-02-05
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Expires: 2003-10-24
Abstract
Abstract The invention provides a unique sub-micron dimensioned resistor and methods of making the same, wherein hundreds of such resistors may be fabricated on a single chip with each comprising an active region surrounded by field oxide completely isolating it from the substrate and its effects on operation. Spaced apart slots made in the substrate permit the introduction of orientation dependent etching fluid therein to at least substantially etch semi-arrays of active regions of the substrate away from the substrate except for spaced apart supports therealong. Oxidation serves to support the semi-arrays and subsequent steps directly from the substrate or by webs of oxidation along the tops of the semi-arrays connected to the substrate. The support is necessary while orthogonal slots are provided permitting access to opposed sides of the active regions for doping from each end, which doping is driven in from both sides to provide a resistor active region to which electrical connections are applied using conventional techniques providing almost complete reduction of the parasitic capacitances because of the total oxide isolation of the active regions from the substrate. The resistors may also be made by forming intersecting slots in spaced apart relation across the substrate to define semi-arrays of V shaped intermediate regions which will become resistors. Silicon oxide fills these slots and separates the resistor regions from the substrate. Orthogonal slots divide the semi-arrays into individual resistor active regions which are optionally doped by one of N or P doping introduced into each active regions via the orthogonal slots and driven in to comprise the resistors.
Inventors
- 👤 Sidney I. Soclof
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 18:19
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/40; H10D1/43; H10D84/00; H10D84/201; H10D84/204; H10D84/206; H10D84/209; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/014; H10W10/0148; H10W10/10; H10W10/17; Y; Y10; Y10S; Y10S438/00; Y10S438/98
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
150 words
A method for forming an array of sub-micron dimensioned resistors on a doped substrate, wherein each resistor is formed comprising the following steps: masking the substrate to outline a pair of boundary regions for each semi-array of active regions to become resistors; slotting the substrate in said boundary regions to a given depth; etching away the substrate via said slots sufficiently to separate the semi-arrays of active regions from the substrate except at spaced apart supporting locations therealong; oxidizing the substrate and semi-arrays to at lease substantially completely oxidize the peripheries of the semi-arrays; slotting the substrate orthogonally to the first mentioned slots to provide second slots with orthogonal pairs of slots defining individual transistor active regions for the respective transistors; optionally doping the regions defined by orthogonal pairs of slots via corresponding edges of the second slots and driving in the doping; and, establishing electrical connections to the regions.
Claim 2
Independent Claim
150 words
A method for forming an array of sub-micron dimensioned resistors on a doped substrate, wherein each resistor is formed comprising the following steps: masking the substrate to outline a pair of boundary regions for each semi-array of active regions to become resistors; slotting the substrate in said boundary regions to a given depth; etching away the substrate via said slots sufficiently to separate the semi-arrays of active regions from the substrate except at spaced apart supporting locations therealong; oxidizing the substrate and semi-arrays to at lease substantially completely oxidize the peripheries of the semi-arrays; slotting the substrate orthogonally to the first mentioned slots to provide second slots with orthogonal pairs of slots defining individual transistor active regions for the respective transistors; optionally doping the regions defined by orthogonal pairs of slots via corresponding edges of the second slots and driving in the doping; and, establishing electrical connections to the regions.
Claim 3
Dependent Claim
15 words
The method of claim 1, wherein: said etching is accomplished by orientation dependent etching fluid.
Claim 4
Dependent Claim
17 words
The method of claim 1 wherein: each active region is supported from the substrate by substrate oxide.
Claim 5
Dependent Claim
22 words
The method of claim 1 wherein: the active regions are supported from the substrate by webs of oxide along the top thereof.
Claim 6
Dependent Claim
28 words
The method of claim 1 wherein: the substrate is P+ type and the upper surface thereof is [100] oriented with the surfaces remaining after etching being [111] oriented.
Claim 7
Independent Claim
125 words
A method for producing an array of sub-micron dimensioned resistors formed on a doped silicon substrate comprising the steps of: forming a plurality of first sidewalls of pairs of intersecting slots in spaced apart relation across the substrate defining semi-arrays of V shaped intermediate regions which will become resistors; oxidizing the substrate and intermediate regions to fill said slots and cover the surface of the substrate through which they were made; forming a plurality of second sidewalls of orthogonal slots relative to said pairs of slots dividing the semi-arrays of regions into individual resistor active regions; doping each of said active regions via said second sidewalls; driving in said doping to comprise changed resistive regions; and, forming metallization patterns in electrical connection with the regions.
Claim 8
Independent Claim
125 words
A method for producing an array of sub-micron dimensioned resistors formed on a doped silicon substrate comprising the steps of: forming a plurality of first sidewalls of pairs of intersecting slots in spaced apart relation across the substrate defining semi-arrays of V shaped intermediate regions which will become resistors; oxidizing the substrate and intermediate regions to fill said slots and cover the surface of the substrate through which they were made; forming a plurality of second sidewalls of orthogonal slots relative to said pairs of slots dividing the semi-arrays of regions into individual resistor active regions; doping each of said active regions via said second sidewalls; driving in said doping to comprise changed resistive regions; and, forming metallization patterns in electrical connection with the regions.
Claim 9
Independent Claim
123 words
A method for producing an array of sub-micron dimensioned resistors formed on a doped silicon substrate comprising the steps of: forming a plurality of first sidewalls of pairs of intersecting slots in spaced apart relation across the substrate defining semi-arrays of V shaped intermediate regions which will become resistors; oxidizing the substrate and intermediate regions to said slots and over the surface of the substrate through which they were made; a plurality of second sidewalls of orthogonal slots relative to said pairs of slots dividing the semi-arrays of regions into individual resistor active regions; doping each of said active regions via said second sidewalls; driving in said doping to comprise changed resistive regions; and, forming metallization patterns in electrical connection with the regions.
Claim 10
Independent Claim
123 words
A method for producing an array of sub-micron dimensioned resistors formed on a doped silicon substrate comprising the steps of: forming a plurality of first sidewalls of pairs of intersecting slots in spaced apart relation across the substrate defining semi-arrays of V shaped intermediate regions which will become resistors; oxidizing the substrate and intermediate regions to said slots and over the surface of the substrate through which they were made; a plurality of second sidewalls of orthogonal slots relative to said pairs of slots dividing the semi-arrays of regions into individual resistor active regions; doping each of said active regions via said second sidewalls; driving in said doping to comprise changed resistive regions; and, forming metallization patterns in electrical connection with the regions.
Claim 11
Independent Claim
133 words
A method for producing an array of sub-micron dimensioned resistors formed on a silicon substrate doped P or N type, comprising the steps of: forming a plurality of first sidewalls of pairs of intersecting slots in spaced apart relation across the substrate defining semi-arrays of V shaped intermediate regions which will become resistors; silicon oxide filling said slots and covering the surface of the substrate through which they were made; forming a plurality of second sidewalls of orthogonal slots relative to said pairs of slots dividing the semi-arrays of regions into individual resistor active regions; doping of one of N and P each of said active regions via said second sidewalls; driving in said doping to comprise changed resistive values in said regions; and, forming metallization patterns in electrical connection with the regions.
Claim 12
Independent Claim
133 words
A method for producing an array of sub-micron dimensioned resistors formed on a silicon substrate doped P or N type, comprising the steps of: forming a plurality of first sidewalls of pairs of intersecting slots in spaced apart relation across the substrate defining semi-arrays of V shaped intermediate regions which will become resistors; silicon oxide filling said slots and covering the surface of the substrate through which they were made; forming a plurality of second sidewalls of orthogonal slots relative to said pairs of slots dividing the semi-arrays of regions into individual resistor active regions; doping of one of N and P each of said active regions via said second sidewalls; driving in said doping to comprise changed resistive values in said regions; and, forming metallization patterns in electrical connection with the regions.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-02-05 | 1988-08-06 | 1989-02-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-02-05 | 1992-08-06 | 1993-02-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-02-05 | 1996-08-06 | 1997-02-05 | $7700.00 | Window Closed / Lapsed |