Anti-wheel-lock control system

Claim 1

An anti-wheel-lock control system for vehicles comprising a wheel speed transducer (1) providing actual wheel speed signals, and, upon oscillating operation of wheels, disturbance signals; an evaluation circuit (3) coupled to the speed transducer and receiving signals therefrom, and generating control signals; devices (4, 5) coupled to the evaluation circuit for varying braking pressure; and a network to recognize disturbance signals occurring due to frictional oscillations of the wheels and inhibiting said disturbance signals from affecting operation of the evaluation circuit (3) comprising means (16a, b max ; 28, B, 28', B') for setting a simulation signal which has a range corresponding to a change in wheel speed which is physically impossible; recognition circuit means (15-17; 22, 27, 29) comparing the wheel speed signals with the simulation signals and providing an output if the wheel speed signals include disturbance signals which represent physically impossible conditions in the system and hence are within the range of the simulation signals; a memory (18; 24) including an integrator continuously storing wheel speed signals as received from the transducer and providing auxiliary wheel speed signals; and an auxiliary device (13, 17; 30) connected to and controlled by said recognition circuit means and inhibiting application of signals from the transducer (1) to the evaluation circuit and, instead, connecting the storage means to the evaluation circuit to provide auxiliary wheel speed signals for the control devices (4, 5) from wheel speed measured prior to appearance of the disturbance in the signals derived from the transducer (1); and wherein, for digital processing of signals in the system, the transducer (1) provides output signals in pulse form; a first counter (22) is provided; means (23) for setting the first counter to a predetermined count value comprising a number entering means (23) which sets said first counter (22) to a predetermined count value, said first counter counting down from said predetermined count value; control means (24) coupled to the counter and changing the count value therein at a rate representative of the count number set into the counter upon occurrence of a preceding pulse from the transducer, so that the count number counted by the counter, upon no change in wheel speed, will be unvarying, the counter control means including said integrator (24) and a number-frequency converter to provide numbered pulses to said first counter (22) and to control the counting state of said first counter, said integrator controlling the first counter to count down at a frequency which is in proportion with a previously measured speed value as counted by said counter and controlled by said integrator (24), the pulses from the integrator so controlling the first counter (22) that, when wheel speed is unvarying, said first counter is placed into zero position until the appearance of a next transducer pulse; a count value decoder (25) is provided, connected to the first counter for decoding the count value deviation (A) from zero of said counter, said count value decoder being connected to said integrator (24) in a closed loop to correct the integration rate of said integrator so that, upon a subsequent cycle of the counter when trigered by a speed signal from the transducer, and under then unvarying wheel speed conditions, the counter will then again count to zero; and wherein the recognition circuit means comprises a digital comparator (27) comparing the actual count state (A) of said first counter (22) with a count value derived from said simulation signal setting means and providing a count state representative of a physically impossible condition in the system, said comparator providing an output signal representative of the comparison of the number (A) in the counter and the threshold (B, B') supplied thereto by said simulation signal setting means; and wherein a gate circuit (29, 30), forming said auxiliary device, is provided, coupled to said count decoder (25) and the integrator (24) and rendering change in the integrator ineffective if the count state in the first counter (22) exceeds said threshold (B) applied thereto by the simulation signal generating means (28), the integrator thereby maintaining the wheel speed signal as an auxiliary stored wheel speed signal representative of prior wheel speed.