CMOS scannable latch

Claim 2

A scannable latch circuit for selectively handling data bit signals under control of at least one clock signal, said scannable latch circuit comprising: latch means, operable in a first mode of operation, for providing and maintaining a data output bit signal for an entire clock cycle of a first clock signal, said data output bit signal being equivalent to a data input signal immediately preceding said clock cycle, said latch means comprising a first circuit connected in tandem to a second latch circuit, said first and second latch circuits operating respectively as master and slave latch circuits during said first mode of operation; shift means, operable in a second mode of operation, for selectively allowing data bit signals to be shifted into and out of said latch means, said shift means including output means for shifting data out of said latch means that is isolated from the data output bit signal provided by said latch means in said first mode of operation, said shift means comprising a third latch circuit coupled to said second latch circuit, said second and third latch circuits operating respectively as master and slave latch circuits during said second mode of operation; and select means for selecting the mode of operation of said scannable latch circuit, said select means being operable during all useful portions of said clock cycle.

Claim 3

A scannable latch as defined in claim 1 wherein said shift means comprises: means for maintaining said first clock signal in a prescribed state, thereby suspending the clocking of said first mode of operation; means for allowing a shift-in bit signal to be clocked into said second latch circuit in response to a second clock signal; and means for allowing the contents of said second latch circuit to be clocked into said third latch circuit in response to a third clock signal; whereby the clocking of said latch means of said first mode of operation may be suspended at any time, and the contents of said second latch circuit may be selectively altered using the shift means of said second mode of operation.

Claim 4

A scannable latch as defined in claim 2 wherein said select means comprises: means for chopping said first clock signal so that it assumes a first of two possible states for only a short period of time compared to the time it assumes a second of said possible states, a clock transition from said first state to said second state being that transition which causes an output of the first latch circuit to be transferred to the second latch circuit during said first mode of operation; means for selectively applying said second clock signal to said shift-in bit means; and means for selectively applying said third clock signal to said third latch circuit.

Claim 5

A scannable latch as defined in claim 3 wherein said chopping means comprises a logic gate having at least two inputs, each of which is coupled to said first clock signal, but through means that introduce different time delays, if any, in the propagation of said clock signal to the respective inputs of said gate.

Claim 6

A scannable latch as defined in claim 4 wherein said first, second, and third clock signals are all derived from a common master clock signal.

Claim 7

An improved CMOS combination latch and shift register circuit comprising, three latch circuits, each having an input and an output, the output of a first of said three latch circuits being connected to the input of a second of said three latch circuits, and a third of said three latch circuits being coupled to the output of the second latch circuit; transmission gate means coupled to said second latch circuit for selectively allowing data to be entered in said second latch circuit over a shift-in input line; and a clock means for selectively providing a plurality of clock signals that control the operation of said first, second, and third latch circuits and said transmission gate means, said clock means comprising a first clock signal being coupled to said first and second latch circuits and being adapted to operate said circuits as a master/slave latch, the first latch circuit functioning as a master section of said master/slave latch, and the second latch circuit functioning as a slave section of said master/slave latch, a second clock signal being coupled to said second latch circuit and being adapted to clock data appearing on the shift-input line into the second latch circuit, and a third clock signal being coupled to said third latch circuit and being adapted to clock data into the third latch circuit from second latch circuit; whereby, in a first mode of operation, wherein said first clock signal is enabled and said second and third clock signals are disabled, said CMOS combination circuit may operate as a master/slave latch circuit wherein the input of said master/slave latch circuit is the input of the first latch circuit, and the output of said master/slave latch circuit is the output of the second latch circuit; and further whereby, in a second mode of operation, wherein said first clock signal is disabled and said second and third clock signals are enabled, said CMOS combination circuit may operate as a shift register circuit wherein the input of said shift register circuit is the shift-in line of said transmission gate means, and the output of said shift register circuit is the output of said third latch circuit.

Claim 8

An improved CMOS combination latch and shift register circuit comprising, three latch circuits, each having an input and an output, the output of a first of said three latch circuits being connected to the input of a second of said three latch circuits, and a third of said three latch circuits being coupled to the output of the second latch circuit; transmission gate means coupled to said second latch circuit for selectively allowing data to be entered in said second latch circuit over a shift-in input line; and a clock means for selectively providing a plurality of clock signals that control the operation of said first, second, and third latch circuits and said transmission gate means, said clock means comprising a first clock signal being coupled to said first and second latch circuits and being adapted to operate said circuits as a master/slave latch, the first latch circuit functioning as a master section of said master/slave latch, and the second latch circuit functioning as a slave section of said master/slave latch, a second clock signal being coupled to said second latch circuit and being adapted to clock data appearing on the shift-input line into the second latch circuit, and a third clock signal being coupled to said third latch circuit and being adapted to clock data into the third latch circuit from second latch circuit; whereby, in a first mode of operation, wherein said first clock signal is enabled and said second and third clock signals are disabled, said CMOS combination circuit may operate as a master/slave latch circuit wherein the input of said master/slave latch circuit is the input of the first latch circuit, and the output of said master/slave latch circuit is the output of the second latch circuit; and further whereby, in a second mode of operation, wherein said first clock signal is disabled and said second and third clock signals are enabled, said CMOS combination circuit may operate as a shift register circuit wherein the input of said shift register circuit is the shift-in line of said transmission gate means, and the output of said shift register circuit is the output of said third latch circuit.

Claim 9

A combination latch and shift register circuit as defined in claim 6 wherein said first, second and third latch circuits each comprise: first and second inverter gates connected in tandem, the mid-point of said inverter gate tandem connection, that is the point where the output of the first inverter gate is connected to the input of the second inverter gate, serving as the output of the respective latch circuit; first and second transmission gates connected in tandem, the midpoint of said transmission gate tandem connection being connected to the input of the first inverter gate, the remaining end-point of said first transmission gate serving as the input of the respective latch circuit, and the remaining end-point of said second transmission gate being coupled to the output of the second inverter gate.

Claim 10

A combination latch and shift register circuit as defined in claim 7 wherein said transmission gate means comprises a third transmission gate and the second inverter gate of said second latch circuit; and a fourth transmission gate having a first end connected to the common connecting point between said second and third transmission gates, and a second end that serves as the shift-in input line.

Claim 11

A combination latch and shift register circuit as defined in claim 8 wherein the input of said third latch circuit is connected to the output of the second inverter gate of said second latch circuit.

Claim 12

A combination latch and shift register circuit as defined in claim 9 wherein: the first transmission gate of the first latch circuit and the second transmission gate of the second latch circuit are turned on, that is, a signal may pass therethrough, whenever said first clock signal assumes a first state, and said same transmission gates are turned off, that is, a signal may not pass therethrough, whenever said first clock signal assumes a second state; the second transmission gate of the first latch circuit and the first transmission gate of the second latch circuit are turned on whenever said first clock signal assumes said second state, and said same transmission gates are turned off whenever said first cock signal assumes said first state; the third transmission gate is turned on and the fourth transmission gate is turned off whenever said second clock signal assumes a first state, and the third transmission gate is turned off and the fourth transmission gate is turned on whenever said second clock signal assumes a second state; and the second transmission gate of the third latch circuit is turned on and the first transmission gate of the third latch circuit is turned off whenever the third clock signal assumes a first state, and said same transmission gates are respectively turned off and on whenever the third clock signal assumes a second state.

Claim 13

A combination latch and shift register circuit as defined in claim 10 wherein said first, second, and third clock signals are respectively disabled by maintaining each one in its respective first state.

Claim 14

A combination latch and shift register circuit as defined in claim 11 wherein, during said first mode of operation, said first clock signal assumes its first state for a long time period compared to the time it assumes its second state during each cycle of said first clock.